FMC with NOR FLASH memory

[TOlli]

Hi,

I'm trying to reserve the pins for FMC that would be connected to NOR FLASH. The STM32CubeMX will give me some of the pins, mainly the data lines (FMC_D0:FMC_D15) for 16 bit data.

Since the reference manual states that FMC has to be configured after reset, I have to manually pick the address pins (FMC_A0:FMC_A25).

Couple of questions regarding this, as I did not find these questions from the documentation:

1. Do I have to pick any other pins manually?
2. What is the difference in nomenclature with FMC_AD6 and FMC_D6 as they are tied to the same pin?
3. Am I correct to assume that the FMC connected memory is memory mapped and I'm able to read and write to it during execution? I just want to make sure as this is not the case with QSPI in memory mapping mode.

Thank you!

-Tero

[PatrickF]

Currently, our SW and Tools deliveries for STM32MP1 series only support FMC with NAND on Linux (Cortex-A7 side). No support of FMC on Cortex-M4.

Nothing planned to deliver more, so you need to assume some custom development on your side.

Note that in all cases, using FMC with NAND on Linux will avoid simultaneous usage for other purposes.

Adding FMC NOR Flash or SRAM support on Linux will required that you build a new driver which is probably a complex task.

Adding FMC support on Cortex-M4 side is probably easier by e.g. porting STM32H7 FMC HAL to STM32MP15 (FMC IP is very similar, except for NAND management).

You should manually configure pin muxing in your SW as currently, pin setting outside FMC NAND signals are not available.

When initialized, FMC is memory mapped for SRAM/NOR (as for QSPI), but obviously, only for read when used with a NOR Flash. Programming sequence should be handled by your driver/HAL.

Note that even if memory mapped, we did not recommend using FMC (or QSPI) for Cortex-M4 code execution due to very poor expected performances due to clock domain crossing and lack of cache mechanism on Cortex-M4.

FMC_ADx and FMC_Dx are tied on same pin, only difference is that ADx carry Address and Data when used with ADMux external devices.

[TOlli]

Hi Patrick

So what I'm reading here, I should be looking to switch to NAND Flash for the FMC at least.

The Cortex-M4 is only going to be handling exceptions from HW so hopefully the code will fit into the existing onboard RAM.

Can you advise me on than if my setup is viable:

* We have 1GB of DDR on the board for A7 code execution

* I will add NAND Flash to the FMC to act as a non-volatile memory (we would store our program code here)

* Boot code to setup the device would be on QSPI NOR FLASH

My initial idea was to use QSPI NOR FLASH to boot the device and setup FMC to load the program code. All code would be executed in DDR. Periodically or when a new setpoint/parameter value is catched during code execution, I would write that value in the NAND Flash.

Would it be easier/more efficient to set this up with using SDMMC memory peripheral instead of the FMC NAND FLASH? This under the assumptions that I run out of available pins as I do need some of the other peripherals as well.

Best regards and thank you for your help,

Tero

[PatrickF · Accepted solution]

Hi,

This QSPI NOR + FMC NAND setup is already supported on our STM32MP157C-EV1 board, and you will find all HW relevant setting example using STM32CubeMX with this board.

The complete SW example, including binary and flashlayouts is available in Starter Package. You could also have a look to https://wiki.st.com/stm32mpu/wiki/STM32CubeProgrammer_flashlayout#NOR_and_NAND_Flash_memories.

Other setups like QSPI NOR + SDCMMC2 eMMC is also supported.

You have Linux image + user data on different partitions of a single NAND or eMMC. see https://wiki.st.com/stm32mpu/wiki/STM32MP15_Flash_mapping