STM32MP257DAI3 and LPDDR4 Impedance Recommendation

[apinales]

I am working on a design using the STM32MP257DAI3 and LPDDR4 memory. During the layout phase I was reviewing the routing guidelines from an5724. Section 6.3 recommends the following controlled impedances are required for the LPDDR4 interfaces:

• for single-ended signals: 55 Ω ±10%.
• for differential signals: 100 Ω differential ±10%

Can ST help me understand why they recommend 55 and 100 specifically for STM32MP257DAI3 with LPDDR4 and not 45 ohm single-ended and 85 ohm differential, which is what many 3rd parties seem to be proposing? 

[PatrickF]

Hi @apinales 

I'm not PCB expert, but I know the rationale is to have narrow PCB track (e.g. depending on ball pitch, to being able to route 1 or 2 tracks in between two balls while keeping good clearance).

We recommend to stick to our values as all LPDDR4 settings and STM32MP2 characterizations are based on those. It could be tricky to changes.

Regards.

[apinales]

Hi Patrick, in addition to the target impedance, trace widths are also impacted by the final board stack-up. So in theory it is possible to use STM's recommended impedance targets for the LPDDR4 interface, and not have enough clearance to break the signals out.

I'm mainly wondering why there seems to be a non-negligible difference in what STM recommends for the LPDDR4 interface compared to 3rd party LPDDR4 design guidelines for their respective chipset. Does the reason have something to do with STM32MP257DAI3 LPDDR4 controller implementation or settings?

[PatrickF]

Hi,

Rationale is as I have listed (get track width suitable for our boards).

Not linked to controller, but as all of our characterizations and tests are made only with those impedance, I would strongly recommend to stick to this to avoid clever changes on the DDRPHY settings requiring strong expertise.

Btw, we provides pre-routed LPDDR4 Altium project examples for all packages: STM32MP2 Series DDR memory routing guidelines examples .

Regards.