STM32MP157DAC EVB: DDR3L Length Matching

[Gaja]

Hi,

I am referring to the STM32MP157D-DK1 EVB (STM32MP157DAC1), specifically the "mb1272-bdp" design file, and would like to clarify the correct method for measuring DDR3L to Microprocessor (MP) trace lengths on the PCB.

My question is regarding the Clock P/N signals:

Should the PCB trace length be measured from the MP pin to the DDR3L chip clock pin (CK_P/N), or from the MP pin to the 100 Ω termination resistor? The reason for the question is that the termination is placed after the DDR3L chip, which adds additional trace length.

After reviewing the EVB design (mb1272-bdp design file) and analyzing the trace lengths using the ST-provided length equalization Excel file, I have the following observations:

1. When measuring trace length from the MP pin to the DDR3L chip pin:

   • The address group signals are mostly within acceptable limits, except for A16, RAS, and A0.

   • However, the data strobe signals (DQS P/N) are outside the required −15 mm to 0 mm range with respect to the clock signal.

Address Group:

The Data groups (DSQ P/N):

2. When measuring trace length from the MP pin to the clock termination resistor:

• The address group signals show multiple mismatches.

• The data strobe signals (DQS P/N) fall within the acceptable range.
  Address group:

The Data groups (DSQ P/N) are okay:

We have followed the trace length guidelines of the EVB for our custom board design. Therefore, we would greatly appreciate your guidance on which method of trace length measurement should be followed to validate the DDR3L layout correctly.
Could you please confirm if using the same trace lengths as the STM32MP157D-DK1 EVB (MB1272-BDP) is acceptable for a custom design? We would prefer not to deviate from the EVB implementation, since it is known to work reliably, unless a deviation is absolutely necessary.

Thank you!

[Gaja]

Following up on the above query, could you get a chance to look?

[Gaja]

Could you please reply to the above query? Thanks!

[Zakaria1]

Hello @Gaja,

Since the expert who can answer your question is on leave and will return next week, I’ll reach out to them as soon as they’re back and keep you updated in the post.

Best Regards,
Zakaria

[Gaja]

Hi Zakaria,

I am waiting for your reply. Actually, I would like to release the Gerber after clarifying this above query, so could you please reply as soon as possible?

Thanks!

Regards,

Gaja

[Zakaria1]

Hello @Gaja,

Should the PCB trace length be measured from the MP pin to the DDR3L chip clock pin (CK_P/N), or from the MP pin to the 100 Ω termination resistor?
Awnser : from the MP pin to the DDR3L chip clock pin (CK_P/N).

- The address group signals are mostly within acceptable limits, except for A16, RAS, and A0.
The measurements of the DK MP15 board show some values slightly outside the limits, but this is due to the Altium version used (A6 is out of spec, but it was validated as is). The Altium version used for designing this board is very old.
If you want, you can copy the DK’s design, as it passes JEDEC tests.

It seems that the measurements for the Address/Command do not include the via lengths on your side for the  Address Group: Section 1.
As for the Data, I’m not sure why there’s a 500/600-micron discrepancy between your measurements and those below.
Here are images showing the address and data signal lengths of the DK board, measured with Altium Rev 24.
I hope this answers your questions.

Best Regards,
Zakaria