Request for Official Documentation on Internal Pin Lengths for DDR Design

[MGrod]

Hello ST team and community,

Why doesn’t ST provide the necessary internal pin length information for DDR layout in an official and accessible way — such as in the datasheet, an application note, or any other verified documentation?

Currently, the only resource available is an Excel table listing signal names, not pin names, and as far as I can tell, it’s based on an Altium reference design. While it's theoretically possible to map signal names to actual pins, there is no reliable way to verify this mapping — especially since the Excel file isn't an official part of the datasheet or app notes.

This makes accurate DDR layout challenging, especially for length matching, where precise internal pin delay data is critical.

I kindly ask ST to provide official documentation that includes internal pin lengths clearly referenced by actual pin names, not just signal names.

This would make DDR layout far more reliable and would prevent design issues caused by guesswork or reverse-engineering unofficial materials.

Thank you in advance.

[MGrod]

Sorry if this comes across as a bit irritated — it's just frustrating that such important information isn’t provided clearly, even though it’s obviously known internally.

[MGrod]

Hello ST team, just a gentle follow-up to see if there’s any update on this.

[MGrod · Accepted solution]

I received an official reply on this after two weeks of waiting....



"This excel sheet is mentioned is THE reference for internal length DDR track and is used for track length equalization.

This is covered in ST AN5122 5.2 Length equalization chapter.

"ST templates and length equalization tables can be used to help simplify the task of equalizing signal trace lengths. These tables include the trace lengths of the packages."

In the excel sheet, the signal name X ("net name") refers to the DDR_X pin name in the data sheet, there is no ambiguity possible."