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scarthgap STM32MP157 PMIC no DDR VDD (buck2) output

Makandra
Associate II

Hello

I have a cutom board based on STM32MP157D-EV1.

The dts is based on stm32mp157f-ed1.dts with minor differences:

* HSE: Bypass -> crystal (There is a 24MHz crystal). Removed "st,digbypass;" from &clk_hse

* DDR: 32bit 8Gb -> 16bit 4Gb. (Using MT41K256M16TW-107). Change the included ddr.dtsi to #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"

 

When flashing, I get this error: ERROR: DDR addr bus test: can't access memory @ 0xc0000004

I can see that the 1.35V does never ouput from BUCK2 of the PMIC, so I assume that the origin of the issue is there. I have modified the tf-a code to add traces and can see that buck2 should indeed be enabled. 

The HW works: I have run another build based on kirkstone on the same HW.

 

I am running out of ideas of where to look next. Does anyone have any ideas?

 

The dts:

 

Spoiler
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) /* * Copyright (C) STMicroelectronics 2022 - All Rights Reserved * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. */ /dts-v1/; #include "stm32mp157.dtsi" #include "stm32mp15xd.dtsi" #include "stm32mp15-pinctrl.dtsi" #include "stm32mp15xxaa-pinctrl.dtsi" #include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" / { model = "STMicroelectronics STM32MP157D XXX"; compatible = "st,stm32mp157d-ed1", "st,stm32mp157"; chosen { stdout-path = "serial0:115200n8"; }; memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x20000000>; }; aliases { serial0 = &uart4; }; }; &bsec { board_id: board_id@ec { reg = <0xec 0x4>; st,non-secure-otp; }; }; &clk_hse { }; &cpu0 { cpu-supply = <&vddcore>; }; &cpu1 { cpu-supply = <&vddcore>; }; &ddr { vdd-supply = <&vdd_ddr>; vtt-supply = <&vtt_ddr>; vref-supply = <&vref_ddr>; }; &fmc { pinctrl-names = "default"; pinctrl-0 = <&fmc_pins_a>; status = "okay"; nand-controller@4,0 { status = "okay"; nand@0 { reg = <0>; nand-on-flash-bbt; #address-cells = <1>; #size-cells = <1>; }; }; }; &hash1 { status = "okay"; }; &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; status = "okay"; pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; status = "okay"; regulators { compatible = "st,stpmic1-regulators"; ldo1-supply = <&v3v3>; ldo2-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>; ldo5-supply = <&v3v3>; ldo6-supply = <&v3v3>; pwr_sw1-supply = <&bst_out>; pwr_sw2-supply = <&bst_out>; vddcore: buck1 { regulator-name = "vddcore"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; }; vdd_ddr: buck2 { regulator-name = "vdd_ddr"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; }; vdd: buck3 { regulator-name = "vdd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; st,mask-reset; regulator-initial-mode = <0>; regulator-over-current-protection; }; v3v3: buck4 { regulator-name = "v3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-over-current-protection; regulator-initial-mode = <0>; }; vdda: ldo1 { regulator-name = "vdda"; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; }; v2v8: ldo2 { regulator-name = "v2v8"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; }; vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; regulator-always-on; regulator-over-current-protection; st,regulator-sink-source; }; vdd_usb: ldo4 { regulator-name = "vdd_usb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; vdd_sd: ldo5 { regulator-name = "vdd_sd"; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; regulator-boot-on; }; v1v8: ldo6 { regulator-name = "v1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; }; bst_out: boost { regulator-name = "bst_out"; }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; regulator-active-discharge = <1>; }; }; }; }; &iwdg1 { timeout-sec = <32>; status = "okay"; }; &pwr_regulators { vdd-supply = <&vdd>; vdd_3v3_usbfs-supply = <&vdd_usb>; }; &qspi { pinctrl-names = "default"; pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: mx66l51235l@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; #address-cells = <1>; #size-cells = <1>; }; }; &rcc { compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon"; st,clksrc=< CLK_MPU_PLL1P CLK_AXI_PLL2P CLK_MCU_PLL3P CLK_MCO1_DISABLED CLK_MCO2_DISABLED CLK_CKPER_HSE CLK_FMC_ACLK CLK_QSPI_ACLK CLK_ETH_PLL4P CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE CLK_USBPHY_HSE CLK_SPI2S1_PLL3Q CLK_SPI2S23_PLL3Q CLK_SPI45_HSI CLK_SPI6_HSI CLK_I2C46_HSI CLK_SDMMC3_PLL4P CLK_USBO_USBPHY CLK_ADC_CKPER CLK_CEC_LSE CLK_I2C12_HSI CLK_I2C35_HSI CLK_UART1_HSI CLK_UART24_HSI CLK_UART35_HSI CLK_UART6_HSI CLK_UART78_HSI CLK_SPDIF_PLL4P CLK_FDCAN_PLL4R CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q CLK_SAI4_PLL3Q CLK_RNG1_CSI CLK_RNG2_LSI CLK_LPTIM1_PCLK1 CLK_LPTIM23_PCLK3 CLK_LPTIM45_LSE >; st,clkdiv = < DIV(DIV_MPU, 1) DIV(DIV_AXI, 0) DIV(DIV_MCU, 0) DIV(DIV_APB1, 1) DIV(DIV_APB2, 1) DIV(DIV_APB3, 1) DIV(DIV_APB4, 1) DIV(DIV_APB5, 2) DIV(DIV_MCO1, 0) DIV(DIV_MCO2, 0) >; st,pll_vco { pll2_vco_1066Mhz: pll2-vco-1066Mhz { src=<CLK_PLL12_HSE>; divmn = <2 65>; frac = <0x1400>; }; pll3_vco_417Mhz: pll3-vco-417Mhz { src=<CLK_PLL3_HSE>; divmn = <1 33>; frac = <0x1a04>; }; pll4_vco_594Mhz: pll4-vco-594Mhz { src=<CLK_PLL4_HSE>; divmn = <3 98>; }; }; /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ pll2: st,pll@1 { compatible = "st,stm32mp1-pll"; reg = <1>; st,pll = <&pll2_cfg1>; pll2_cfg1: pll2_cfg1 { st,pll_vco = <&pll2_vco_1066Mhz>; st,pll_div_pqr = <1 0 0>; }; }; /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ pll3: st,pll@2 { compatible = "st,stm32mp1-pll"; reg = <2>; st,pll = <&pll3_cfg1>; pll3_cfg1: pll3_cfg1 { st,pll_vco = <&pll3_vco_417Mhz>; st,pll_div_pqr = <1 16 36>; }; }; /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; st,pll = <&pll4_cfg1>; pll4_cfg1: pll4_cfg1 { st,pll_vco = <&pll4_vco_594Mhz>; st,pll_div_pqr = <5 7 7>; }; }; }; &rng1 { status = "okay"; }; &rtc { status = "okay"; }; &sdmmc1 { pinctrl-names = "default"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; disable-wp; st,sig-dir; st,neg-edge; st,use-ckin; bus-width = <4>; vmmc-supply = <&vdd_sd>; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-ddr50; status = "okay"; }; &sdmmc2 { pinctrl-names = "default"; pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; non-removable; no-sd; no-sdio; st,neg-edge; bus-width = <8>; vmmc-supply = <&v3v3>; vqmmc-supply = <&vdd>; mmc-ddr-3_3v; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; status = "okay"; };
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1 REPLY 1
Makandra
Associate II

Hello

I found a way forward:

In stm32mp_pmic.c,

void initialize_pmic(void) { if (!initialize_pmic_i2c()) { VERBOSE("No PMIC\n"); return; } register_pmic_shared_peripherals(); if (register_pmic() < 0) { panic(); } //Remove these lines and buck2 will enable the output //if (stpmic1_powerctrl_on() < 0) { // panic(); // } }

 

I did not make up the solution, I found it from an inherited project. Does anyone have any explaination to why this works?