Device Tree configuration for RMII with Crystal on PHY, no 50Mhz from PHY

[TStru.1]

I am attempting to configure my device tree to support RMII with Crystal on PHY, no 50Mhz from PHY. I have made the following modifications based on https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RGMII_with_Crystal_on_PHY-2C_no_125Mhz_from_PHY with a 50MHz clock instead of 125Mhz.

Board Specific Linux DTS

&ethernet0 {
	status = "okay";
	pinctrl-0 = <&eth1_pins_mx>;
	pinctrl-1 = <&eth1_sleep_pins_mx>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rmii";
	max-speed = <100>;
	phy-handle = <&phy0>;
 
	mdio0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dwmac-mdio";
 
			phy0: ethernet-phy@0 {
				reg = <0>;	
				reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
				reset-assert-us = <1000>;
				reset-deassert-us = <200000>;
			};
	};
};

stm32mp151.dtsi

ethernet0: ethernet@5800a000 {
	compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
	reg = <0x5800a000 0x2000>;
	reg-names = "stmmaceth";
	interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
							<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
							<&exti 70 1>;
	interrupt-names = "macirq",
						"eth_wake_irq",
						"stm32_pwr_wakeup";
	clock-names = "stmmaceth",
					"eth-ck",
					"mac-clk-tx",
					"mac-clk-rx",
					"ethstp";
	clocks = <&rcc ETHMAC>,
				<&rcc ETHCK_K>,                
				<&rcc ETHTX>,
				<&rcc ETHRX>,
				<&rcc ETHSTP>;
	st,syscon = <&syscfg 0x4>;
	snps,mixed-burst;
	snps,pbl = <2>;
	snps,en-tx-lpi-clockgating;
	st,eth-clk-sel;
	snps,axi-config = <&stmmac_axi_config_0>;
	snps,tso;
	power-domains = <&pd_core>;
	status = "disabled";
};

TF-A dts rcc

&rcc {
	st,csi-cal;
	st,hsi-cal;
	st,cal-sec = <60>;
	st,clksrc = <
		CLK_MPU_PLL1P
		CLK_AXI_PLL2P
		CLK_MCU_PLL3P
		CLK_PLL12_HSE
		CLK_PLL3_HSE
		CLK_PLL4_HSE
		CLK_RTC_LSE
		CLK_MCO1_DISABLED
		CLK_MCO2_DISABLED
	>;
	st,clkdiv = <
		1 		/*MPU*/
		0 		/*AXI*/
		0 		/*MCU*/
		1 		/*APB1*/
		1 		/*APB2*/
		1 		/*APB3*/
		1 		/*APB4*/
		2 		/*APB5*/
		0 		/*RTC*/
		0 		/*MCO1*/
		0 		/*MCO2*/
	>;
	st,pkcs = <
		CLK_CKPER_HSE
		CLK_ETH_PLL4P /*CLK_ETH_DISABLED*/
		CLK_SDMMC12_PLL4P
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_SPI2S1_DISABLED
		CLK_SPI2S23_PLL3Q
		CLK_SPI45_DISABLED
		CLK_SPI6_DISABLED
		CLK_I2C46_HSI
		CLK_SDMMC3_DISABLED
		CLK_USBO_USBPHY
		CLK_ADC_CKPER
		CLK_CEC_DISABLED
		CLK_I2C12_HSI
		CLK_I2C35_DISABLED
		CLK_UART1_DISABLED
		CLK_UART24_HSI
		CLK_UART35_DISABLED
		CLK_UART6_DISABLED
		CLK_UART78_DISABLED
		CLK_SPDIF_DISABLED
		CLK_FDCAN_HSE
		CLK_SAI1_DISABLED
		CLK_SAI2_DISABLED
		CLK_SAI3_DISABLED
		CLK_SAI4_DISABLED
		CLK_LPTIM1_DISABLED
		CLK_LPTIM23_DISABLED
		CLK_LPTIM45_DISABLED
	>;
	pll2:st,pll@1 {
		compatible = "st,stm32mp1-pll";
		reg = <1>;
		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
		frac = < 0x1400 >;
	};
	pll3:st,pll@2 {
		compatible = "st,stm32mp1-pll";
		reg = <2>;
		cfg = < 1 33 1 16 36 PQR(1,1,0) >;
		frac = < 0x1a04 >;
	};
	pll4:st,pll@3 {
		compatible = "st,stm32mp1-pll";
		reg = <3>;
		/*cfg = < 3 98 5 7 7 PQR(1,1,0) >;*/
		cfg = < 1 49 11 9 9 PQR(1,1,1) >;
	};
};

I get the following result which I believe indicates a clock configuration error based on section 5.3 of https://wiki.st.com/stm32mpu/wiki/Ethernet_overview

[   17.067472] stm32-dwmac 5800a000.ethernet eth0: PHY [stmmac-0:00] driver [Micrel KSZ8081 or KSZ8091] (irq=POLL)
[   18.094222] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
[   18.098953] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[   18.132868] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed

Is this configuration possible?

[OlivierK]

Hi TStru.1 (Community Member)

In the same page you can find the DT configuration for a RMII configuration with crystal on Phy (3.3.1)

The Ethernet reference clock must come either from RCC or from the 50MHz from the phy to the MAC.

Rgds,

Olivier