Optee panic - custom board with 256 MB ram

[micdini]

Hello,

I'm stalling with an issue with Optee on a custom board with 256 MB of ram and an STM32MP135D.

The environment was working with the DK (MP135F and 512M ram).

I followed the guide for the configuration with 256 MB of ram (https://wiki.st.com/stm32mpu/wiki/How_to_configure_a_256MB_DDR_mapping_from_STM32_MPU_Distribution_Package), however it panics as soon as optee starts.

Am I missing something or do you have some hints?

Thank you

NOTICE:  CPU: STM32MP135D Rev.Y
NOTICE:  Model: STMicroelectronics custom STM32CubeMX board - openstlinux-6.6-yocto-scarthgap-mpu-v24.11.06
ERROR:   nvmem node board_id not found
INFO:    PMIC version = 0x21
WARNING: VDD unknown
WARNING: stm32_rng_init: No RNG found in device tree.
NOTICE:  Reset reason (0x35):
INFO:      Power-on Reset (rst_por)
INFO:    FCONF: Reading TB_FW firmware configuration file from: 0x2ffe0000
INFO:    FCONF: Reading firmware configuration information for: stm32mp_fuse
INFO:    FCONF: Reading firmware configuration information for: stm32mp_io
INFO:    Using SDMMC
INFO:      Instance 1
INFO:    Boot used partition fsbl1
NOTICE:  BL2: v2.10-stm32mp1-r1.0(debug):lts-v2.10.5-dirty(7c229848)
NOTICE:  BL2: Built : 16:19:31, Jun 28 2024
INFO:    BL2: Doing platform setup
INFO:    RAM: DDR3-DDR3L 16bits 533000kHz
INFO:    Memory size = 0x10000000 (256 MB)
INFO:    BL2: Loading image id 1
INFO:    Loading image id=1 at address 0x30006000
INFO:    Image id=1 loaded: 0x30006000 - 0x300061ea
INFO:    FCONF: Reading FW_CONFIG firmware configuration file from: 0x30006000
INFO:    FCONF: Reading firmware configuration information for: mce_config
INFO:    FCONF: Reading firmware configuration information for: dyn_cfg
INFO:    FCONF: Reading firmware configuration information for: stm32mp1_firewall
INFO:    BL2: Loading image id 4
INFO:    Loading image id=4 at address 0xce000000
INFO:    Image id=4 loaded: 0xce000000 - 0xce00001c
INFO:    OPTEE ep=0xce000000
INFO:    OPTEE header info:
INFO:          magic=0x4554504f
INFO:          version=0x2
INFO:          arch=0x0
INFO:          flags=0x0
INFO:          nb_images=0x1
INFO:    BL2: Loading image id 8
INFO:    Loading image id=8 at address 0xce000000
INFO:    Image id=8 loaded: 0xce000000 - 0xce08bfe0
INFO:    BL2: Loading image id 2
INFO:    Loading image id=2 at address 0xc0400000
INFO:    Image id=2 loaded: 0xc0400000 - 0xc040c540
INFO:    BL2: Skip loading image id 16
INFO:    BL2: Loading image id 5
INFO:    Loading image id=5 at address 0xc0000000
INFO:    Image id=5 loaded: 0xc0000000 - 0xc0115bd8
NOTICE:  BL2: Booting BL32
INFO:    Entry point address = 0xce000000
INFO:    SPSR = 0x1d3
I/TC: Early console on UART#2
I/TC:
I/TC: Embedded DTB found
I/TC: OP-TEE version: devtool-patched-1-g082d77e95-dev (gcc version 13.3.0 (GCC)) #15 Thu Jan 29 10:21:24 UTC 2026 arm
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: WARNING: All debug accesses are allowed
E/TC:0 0
E/TC:0 0 Core data-abort at address 0x10 (translation fault)
E/TC:0 0  fsr 0x00000205  ttbr0 0xce0d4000  ttbr1 0x00000000  cidr 0x0
E/TC:0 0  cpu #0          cpsr 0x800001f3
E/TC:0 0  r0 0x00000000      r4 0x00000000    r8 0x00000ac0   r12 0xce09b1b0
E/TC:0 0  r1 0xce0d5f00      r5 0x00000000    r9 0x00000000    sp 0xce0d5ec8
E/TC:0 0  r2 0xce0a8c28      r6 0x7fffffff   r10 0xce08bd6c    lr 0xce04c6ed
E/TC:0 0  r3 0x00000000      r7 0x00000ac0   r11 0xce08bdb4    pc 0xce01b9bc
E/TC:0 0 TEE load address @ 0xce000000
E/TC:0 0 Call stack:
E/TC:0 0  0xce01b9bc
E/TC:0 0  0xce04c6ed
E/TC:0 0  0xce01b9cb
E/TC:0 0  0xce01bbb7
E/TC:0 0  0xce01bf05
E/TC:0 0  0xce01c27b
E/TC:0 0  0xce01f97d
E/TC:0 0  0xce01fa4d
E/TC:0 0  0xce020361
E/TC:0 0  0xce022d85
E/TC:0 0  0xce04a079
E/TC:0 0  0xce00417b
E/TC:0 0  0xce0001a0
E/TC:0 0 Panic 'unhandled pageable abort' at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1/core/arch/arm/kernel/abort.c:593 <abort_handler>
E/TC:0 0 TEE load address @ 0xce000000
E/TC:0 0 Call stack:
E/TC:0 0  0xce0042d9
E/TC:0 0  0xce021e4f
E/TC:0 0  0xce003867
E/TC:0 0  0xce0016e4

[Gregory PLANCHON]

Hi @micdini ,

Are you sure you modified all the components and files ? 

Regards,

Grégory 

[micdini]

Hello,
I tried again several times reinstalling all from scratch.

I found that I was missing the power definition for mmc2

&sdmmc2_io {
	vddsd2-supply = <&vdd_sd>;
};

 
Now I'm trying to start U-Boot but am blocked with this error Violation @0xce025da0, non-secure privileged read, AXI ID 5c0 :

I/TC: Primary CPU switching to normal world boot
F/TC:0   pwr_it_handler:158 
F/TC:0   pwr_it_handler:166 handle wkup irq:0
F/TC:0   pwr_it_call_handler:98 call wkup handler irq:0
F/TC:0   stpmic1_irq_handler:840 Stpmic1 irq handler
F/TC:0   stpmic1_irq_handler:852 Stpmic1 irq pending 1: 0x20
F/TC:0   stpmic1_irq_handler:852 Stpmic1 irq pending 3: 0xc0
F/TC:0   stpmic1_irq_handler:881 Stpmic1 irq handler done
E/TC:0   tzc_it_handler:80 TZC permission failure
E/TC:0   dump_fail_filter:417 Overrun violation on filter 0
E/TC:0   dump_fail_filter:420 Permission violation on filter 0
E/TC:0   dump_fail_filter:425 Violation @0xce025da0, non-secure privileged read, AXI ID 5c0
E/TC:0   Panic at /usr/src/debug/optee-os-stm32mp/4.0.0-stm32mp-r1.2/core/arch/arm/plat-stm32mp1/plat_tzc400.c:84 <tzc_it_handler>
E/TC:0   TEE load address @ 0xce000000
E/TC:0   Call stack:
E/TC:0    0xce00440d
E/TC:0    0xce023a97
E/TC:0    0xce0062a9
E/TC:0    0xce022395
E/TC:0    0xce00d48b
E/TC:0    0xce000388

 Regards,

[GatienC]

Hello,

Have you correctly defined your custom board DDR density in OP-TEE compile options?

I'm thinking of:

CFG_DRAM_BASE ?= 0xc0000000

CFG_DRAM_SIZE ?= 0x40000000

Default is 512Mb so you'd have to specify CFG_DRAM_SIZE=0x20000000 and update your device trees accordingly.

If you are using CubeMX for device tree generation, there is a dedicated section for the DDR density.

Cheers,

Gatien

[loveforcircuits]

First, check CFG_DRAM_SIZE in OP-TEE. It must match 256 MB. Next, update your device tree’s memory@c0000000 node and reserved-memory for OP-TEE.  BL2 and ATF DDR configurations must also reflect the smaller RAM. The secure RAM regions, CFG_TEE_RAM_START, CFG_TEE_RAM_SIZE, and CFG_SHMEM_START, must fit within your 256 MB memory. Overlaps or misalignment cause the pageable abort. ST provides a clear guide for 256 MB DDR mapping explaining these changes. Also, double-check your custom board’s hardware. PCB layout and memory routing can affect DDR stability. STM32 board design tutorial is useful for this. Correct memory mapping in firmware and hardware alignment should resolve the startup panic.

[loveforcircuits]

It looks like your OP-TEE crash is due to memory mapping issues. You reduced RAM from 512 MB to 256 MB, but some settings still assume the larger size. First, check CFG_DRAM_SIZE in OP-TEE; it must match 256 MB. Next, update your device tree’s memory@c0000000 node and reserved-memory for OP-TEE. Ensure BL2 and ATF DDR configurations also reflect the smaller RAM. The secure RAM regions, CFG_TEE_RAM_START, CFG_TEE_RAM_SIZE, and CFG_SHMEM_START, must fit within your 256 MB memory. Overlaps or misalignment cause the pageable abort. ST provides a clear guide for 256 MB DDR mapping explaining these changes. Also, double-check your custom board’s hardware. PCB layout and memory routing can affect DDR stability.

[loveforcircuits]

Here is also a tutorial about making custom boards with STM microcontrollers. 

[Olivier GALLIEN]

Hi @micdini ,

Did you finally fix your problem ? 

Thanks 

Olivier 

[micdini]

Hi, yes I managed to fix my issue.

There was some nodes undefined in op-tee device tree.
But the main issue was I mssed bootph-all in the pinctrl node, so I couldn't see the UART messages from U-Boot.

Thank you and kind regards,