LBEE5KL1DX-883 issue with SDMMC3

[Mahendra Sondagar]

Hi.. there

Hope all are doing well

We have designed our own custom board by taking the reference of the DK2 board, in which we're using the LBEE5KL1DX-883 WiFi/BT module from Murata at SDMMC3

somehow, the module is unable to detect!

after dmesg of the MMC log, I got to know that the SDMMC 3 is not initialized

here is the mmc dmesg logs

[    0.000000] Kernel command line: console=ttySTM0,115200n8 quiet hw_dispid=6 hw_code=143 fastboot=n board_name=ns02_ek435 touch_type= root=/dev/mmcblk0p2 rootfstype=ext4 rootwait
[    0.678302] mmci-pl18x: probe of 48004000.sdmmc failed with error -22
[    0.679283] mmci-pl18x 58005000.sdmmc: Linked as a consumer to regulator.3
[    0.679417] mmci-pl18x 58005000.sdmmc: mmc0: PL180 manf 53 rev2 at 0x58005000 irq 63,0 (pio)
[    0.708451] mmci-pl18x 58007000.sdmmc: Linked as a consumer to regulator.2
[    0.708585] mmci-pl18x 58007000.sdmmc: mmc1: PL180 manf 53 rev2 at 0x58007000 irq 64,0 (pio)
[    0.743212] mmc0: host does not support reading read-only switch, assuming write-enable
[    0.751166] mmc0: new high speed SDHC card at address aaaa
[    0.763214] mmcblk0: mmc0:aaaa JULIE 29.7 GiB 
[    0.789431]  mmcblk0: p1 p2 p3 p4
[    0.790501] mmc1: new high speed MMC card at address 0001
[    0.803767] mmcblk1: mmc1:0001 Q2J55L 7.09 GiB 
[    0.805337] mmcblk1boot0: mmc1:0001 Q2J55L partition 1 16.0 MiB
[    0.806805] mmcblk1boot1: mmc1:0001 Q2J55L partition 2 16.0 MiB
[    0.807161] mmcblk1rpmb: mmc1:0001 Q2J55L partition 3 4.00 MiB, chardev (245:0)
[    0.992158] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[    3.989839] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[   42.152122] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)

From the logs snipped you can see that the mmc initialization is failed with error code 22 !

My DTS file configuration is shown at below

/* WiFi  node */
&sdmmc3 {
    arm,primecell-periphid = <0x10153180>;
    pinctrl-names = "default", "opendrain", "sleep";
    pinctrl-0 = <&sdmmc3_pins_mx>;
    pinctrl-1 = <&sdmmc3_opendrain_pins_mx>;
    pinctrl-2 = <&sdmmc3_sleep_pins_mx>;
    non-removable;
    st,neg-edge;
    bus-width = <4>;
    vmmc-supply = <&v3v3>;
    mmc-pwrseq = <&wifi_pwrseq>;
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
 
 
    brcmf: bcrmf@1 {
        reg = <1>;
        compatible = "brcm,bcm4329-fmac";
    };
};
 
 
//---------------------------------------------------
 
	/* WiFi power ON Sequance from device driver */
	wifi_pwrseq:wifi-pwrseq{
		compatible = "mmc-pwrseq-simple";
		reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;    /* WL_REG_ON        -> PH4 */
	};

right now, I'm deleing with the older BSP without TF-A (4.19.49)

Do I need to set the clock at uboot also?

Can anyone redirect me towards a right solution?

Thanks

[Olivier GALLIEN]

Hi @Mahendra Sondagar​ ,

Did you check you HW by confirming the module is powered and clocked ?

Else could you clarify what you mean by "I'm deleing with the older BSP without TF-A (4.19.49)"

particularly "without TF-A" ? Should I understand Uboot-SPL for so called ( and deprecated) basic boot ?

Else 4.19 is the kernel version of a quite old ecosystem.

Since you are at bring-up level why don't you use the more recent DV3.0 ?

If your design is really a duplication of DK2, the provided BSP might work almost as is.

Olivier

[Mahendra Sondagar]

Hi.. @Community member​ 

Thanks for your feedback

I'm using a 32.768khz external oscillator with my custom board

yes, the board is clocked well, as I have confirmed with the analyzer

I have also confirmed the high to low transaction of the WL_REG pin during the boot time

My kernel version is 4.19.49 without TF-A. it means I have zImage, uboot+spl & rootfs only

yes, you're right it's an older one

But, right now I'm intended to test my application on the existing BSP which I got from my SOM manufacturer because of some strict timeline of the project

here I have attached the screen-shot of the WiFi section of my custom board schematic

Note: WiFi_BT trigger load trigger MOSFET is short at the moment

Thanks & Regards

Mahendra

 

[Olivier GALLIEN]

Hi @Mahendra Sondagar​ ,

First, I kindly warn you that ST is no longer supporting solution based on DV1.2 ( kernel 4.19) moreover using the basic boot which is a non sustainable solution for product development.

If your SOM Maker still provide such solution it's under his responsibility, and it's duty to support you.

This said, I just realized I forgot to ask if you properly enable SDMMC3 kernel clock in U-Boot DT.

You should have in rcc node "st,pkcs" property something like CLK_SDMMC3_PLL4P

Olivier

[Mahendra Sondagar]

Hi.. @Community member​ 

yes, I understood

The SOM design is adopted by taking reference to the DK2 board (except PMIC section)

very soon, I'm going to customize the latest OpenST environment as per our custom board's needs

But for now, I'm looking for the WiFi to be working with the current Linux environment which I have

yes, CLK_SDMMC3_PLL4P is there in uboot DT

st,pkcs = <
		CLK_CKPER_HSE
		CLK_FMC_ACLK
		CLK_QSPI_ACLK
		CLK_ETH_DISABLED
		CLK_SDMMC12_PLL4P
		CLK_DSI_DSIPLL
		CLK_STGEN_HSE
		CLK_USBPHY_HSE
		CLK_SPI2S1_PLL3Q
		CLK_SPI2S23_PLL3Q
		CLK_SPI45_HSI
		CLK_SPI6_HSI
		CLK_I2C46_HSI
		CLK_SDMMC3_PLL4P
		CLK_USBO_USBPHY
		CLK_ADC_CKPER
		CLK_CEC_LSE
		CLK_I2C12_HSI
		CLK_I2C35_HSI
		CLK_UART1_HSI
		CLK_UART24_HSI
		CLK_UART35_HSI
		CLK_UART6_HSI
		CLK_UART78_HSI
		CLK_SPDIF_PLL4P
		CLK_FDCAN_HSE
		CLK_SAI1_PLL3Q
		CLK_SAI2_PLL3Q
		CLK_SAI3_PLL3Q
		CLK_SAI4_PLL3Q
		CLK_RNG1_LSI
		CLK_RNG2_LSI
		CLK_LPTIM1_PCLK1
		CLK_LPTIM23_PCLK3
		CLK_LPTIM45_LSE
	>;

Thanks

Mahendra