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Why the STM32WBA52CG SYSCLK must be 16MHz when the BLE was enabled

Xiaojie
Associate III

HI,All

    I noticed that when we use BLE stack, we must set SYSCLK to 16MHz。When i set the SYSCLK upto 100MHz,the uart1 log will be garbled after call BleStack_Init which contained in st ble stack lib。I don't know if my discovery is correct。I don't understand why ST doesn't provide the source code for the Bluetooth protocol stack。

 

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Hell again @Xiaojie 

The maximum SYSCLK is 100MHz for voltage scaling range 1 and 16Mhz for voltage scaling range 2:

STTwo32_0-1704704596495.png

 

So, to be able to have a SYSCLK up to 100MHz, you need to change the voltage scaling range from 2 to 1:

STTwo32_1-1704704680817.png

Best Regards.

STTwo-32

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5 REPLIES 5
STTwo-32
ST Employee

Hello @Xiaojie 

For the UART problem, I think is related to the Baud rate or other UART configurations.

For the examples, You can take a look at the examples using NUCLEO-WBA55CG.

And you can adapt them to the STM32WBA52CG.

Best Regards.

STTwo-32

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Hi, 

   Thank you for your replay.

    I open a ble_beacon project in STM32Cube_FW_WBA_V1.2.0 which adapted for NUCLEO-WBA55CG。

 

   The default SYSCLK and HCLK1 is 16MHz, when i changed the System Clock Mux to PLLCLK,  Then SYSCLK is up to 64MHz,the STM32CubeMX noticed me that the System Clock must be <= 16MHz。

 

  Why the STM32CubeMX noticed this error?

 

Thanks

 

Hell again @Xiaojie 

The maximum SYSCLK is 100MHz for voltage scaling range 1 and 16Mhz for voltage scaling range 2:

STTwo32_0-1704704596495.png

 

So, to be able to have a SYSCLK up to 100MHz, you need to change the voltage scaling range from 2 to 1:

STTwo32_1-1704704680817.png

Best Regards.

STTwo-32

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Thank you very much!!

HI,

   I notify that the ble stack will modify the RCC configuration。You can see my another issue:

https://community.st.com/t5/stm32-mcus-wireless/ble-stack-modify-the-rcc-configuration/td-p/667539

So if we choose SYSCLK or PCLK2 as usart clock and init the usart befor calling BleStack_Init, the frequency of usart clock will change after calling BleStack_Init. Then the usart will be garbled.

 

Thanks