What is the fastest adc conversion speed using DMA and external trigger based the chip timer peripheral.

[MLiva]

According to manual I should get

Fast channels: 0.234 μs for 12-bit resolution (4.27 Ms/s)

Slow channels: 0.297 μs for 12-bit resolution (3.37 Ms/s)

but I am getting only get 2Ms/s.

I am clocking the chip at 64MHz and using P-NUCLEO-WB55 evaluation board and using a fast channel. I can get faster (3Ms/s) by setting timer counter to 1 (smallest), but the timer will trigger at much faster speeds then the sampling rate achieved.

I am usind STM32CubeMX to configure the device.

[MLiva]

Managed to set the ADC clock to SYSCLK with CubeMX by setting the ADC clock Mux to use SYSCLK. This raised the ADC clock from 48MHz to 64MHz. This now helps to get around 4Ms/s which as per spec. However I still cannot use the timer to control sampling rates above 2Ms/s. So I assume there is a delay introduced from the timer trigger, the DMA data transfer to internal memory when the timer triggers at frequencies above 2Ms/s. When I am setting the timer counter to 1 (smallest) I am generating effectively a 64MHz triggger but I am getting only about 4Mhz ADC sampling rate.

[MLiva]

Looks like this is not a problem is just a limitation. The device can sample up to the rated maximum speed. When the timer is used as a trigger there are not enough timer counters available to resolve all the desired sampling frequencies. So 2MHz can be achieved as 64/2 yields an exact timer counter 32. The timer can then trigger at exactly 2MHz. If I want to raise the sampling to 2.8MHz then 64/2.8=22.85. This is not a integer number. If I set timer counter =22 then the timer will trigger to a different frequency 64/22=2.909MHz which is not 2.8MHz hence me noticing that is not working correctly. So for example I can now confirm that I can get 4.27MHz with a timer counter = 15. This means that the range between 2-4.27MHz can only be supported at specific sampling frequencies around 16 of them.