STM32WL PCB RF Design

[MJaworski]

Dear ST community,
I am developing a PCB design for wireless communication utilizing STM32WLE5CCU6. I have a very basic grasp of RF knowledge, impedance matching for example. I read thoroughly the documents: AN5457 and AN5407 of designing RF layout. I also took a glance on the Nucleo PCB design files. I noticed some discrepancies and I would like to ask you for your insight.

1. In document AN5407 section 9 Table 5 there is example of recommended discontinuity management. It is designed for RF trace width matching the width of SMD components. I checked the STM32WL Nucleo design and noticed that for RFO_LP and RFO_HP signals the traces are quite thick between the matching components. I extracted the trace design properties (width, height, gap, Er) and put them into Saturn PCB calculator. The Zo impedance doesnt match 50 Ohms as shown below:

The Nucleo layout doesn't follow the design rules, as you can see on picture below (I marked a concerning layout with a green rectangle):

The "NETC15_1" trace doesn't have 50 Ohm impedance, and there is a polygon above this net. From the same calculator, the width of trace Matching 50 Ohms impedance should be around 0.155mm. I do understand the fact that the Nucleo design works and was probably a subject of multiple evaluations and checks.

My questions are:
1.how should I deal with discontinuitues between SMD component pad size and trace width (0402 Pad width > trace width), knowing that a rectangular polygon of abstract size related to SMD pads' size works?
2. If I route traces following the guidelines (impedance matched traces expanding their width to match SMD pads) can I still use the C and L values of matching network, or was there some Smith Chart magic included on Nucleo design?

I will highly appreciate any designing tips, I am thankful in advance.

Best regards
Marek Jaworski.

[STTwo-32 · Accepted solution]

Hello @MJaworski 

I've escalated your question internally (under internal ticket number 206960) and the feedback is that you have to follow the layout recommendations and not the NUCLEO-WL55JC1 layout. The NUCLEO-WL55JC1 is an evaluation board. To have the state of art RF optimal design, you have to follow our reference design layout. The main objective of the STM32WL5x and STM32WLEx reference designs is to recommend a layout and associated BOM for dedicated applications. You have to select the reference design based on package, number of layers, SMD or IPD, frequency, output power and RF switch.

Link for our reference design: https://www.st.com/resource/en/data_brief/stdes-wl5u4shw.pdf

In our reference design we don't have these discontinuities between SMD component pad size.

Best Regards.

STTwo-32