Issue was caused by incorrect clocking scheme caused by clock configuration condition race on deep sleep enter/exit. Happens only if 64 MHz PLL used for system clock.
Solution is kinda tricky: core1 is not allowed to perform switch to PLL, instead it must use SHCI_C2_SetSystemClock(available in radio stack 1.17.3 or later) to perform transition. Also if FreeRTOS used then IPCC SYS must be used in blocking mode since interrupts are not available at the moment of transition to stop mode.
