STM32WB55: Maximal execution time running the code on QUADSPI
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‎2022-12-15 4:43 AM
Hi there
How to calculate the maximal possible CPU execution time for the STM32WB55 when running fetching the code from external flash?
Kind Regrads
- Labels:
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QSPI
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STM32WB series
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‎2022-12-15 8:06 AM
Hello @Community member​,
The CPU can execute code from the Quad-SPI memory when using the memory-mapped mode. I advise you to refer to the table 2 of the AN4760 where you can find the maximum QUADSPI speed of STM32WB55, of course added to the datasheet of the product.
Regards,
Chahinez.
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‎2022-12-15 11:02 AM
Dependent on multiple factors.
Not an inherently cached architecture.
Suggest you benchmark with DWT's CYCCNT to evaluate with your own HW, and code construction.
Figure each instruction is 16-bit wide, and you know the QSPI clocking speed, and CS cycles, you can probably put a floor in the execution speed.
Up vote any posts that you find helpful, it shows what's working..
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‎2022-12-16 1:29 AM
Hi all,
Thanks for the quick answers. I did a calculation with this Information for a best case scenario:
- Quadspi: 4 Lane mode
- DDR mode enabled
- SIOO mode enabled (Continuous-read mode)
- Maximum Quadspi clock speed is 50 MHz (AN4760)
- 16-bit instruction length (for 32-bit RISC architecture)
So if we execute a code that contains no jumps, the code can be fetched without sending the address again.
- Per clock we get 2 bit (DDR) per line so 8 bit per clock
- We need 2 clocks to fetch one 16 bit instruction
- So the maximal execution speed would be 25 MHz
Can someone verify this numer for a best case scenario? Are there any necessary wait cycles that I missed?
