Hello everyone.
I am currently trying to implement the application “Phy_802_15_4_Cli” from the STM32Cube repository in Zephyr. We are using a STM32WB55RG. Unlike in the standard application, we use the PLL as SYSCLOCK, the input clock is HSE (32MHz). As CLI (command line interface) we use LPUART. The aim is to use the PC app STM32CubeMonitor-RF with the "Phy_802_15_4_Cli" app on the STM32WB55, which has already worked so far. However, the problem is that in RX mode, as soon as the first 802.15.4 packet is received, the C2DS bit is set in the PWR_EXTSCR register --> “CPU2 is in deepsleep or hold by C2BOOT”. This causes the SW and SWS bits in the RCC_CFGR register to be set from 11 (PLL as system clock) to 10 (HSE as system clock). The output via LPUART then only produces garbage. One way to prevent the low power mode of the C2, e.g. using `SHCI_C2_RADIO_AllowLowPower()` only works with BLE, Thread or Zigbee, but not for the LLD_Tests. Another attempt was to check the SYSCLOCK within the RX callback each time and reset it to PLL if it is not already.
if(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
/* Set PLL as System Clock Source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
}
}
This only works partially, but reduces the garbage in the output. Does anyone have any idea how I can prevent this clock switch?
