I have used STM32Cube_FW_WL_V1.1.0 -> LoRaWAN_FUOTA -> 1_Image sample and build the binary file -> BFU_LoRaWAN_End_Node.bin
After flashing the binary, STM32WL66 Option Bytes got changed and i could not able to erase and update the fflash after that. i tried with mass erase, but it did not help. Please share your inputs to disable the flash write protection.
c:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin>STM32_Programmer_CLI.exe -c port=swd -ob displ
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STM32CubeProgrammer v2.7.0
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ST-LINK SN : 001600345553500B20393256
ST-LINK FW : V3J7M3
Board : NUCLEO-WL55JC
Voltage : 3.26V
SWD freq : 12000 KHz
Connect mode: Normal
Reset mode : Software reset
Device ID : 0x497
Revision ID : Rev Z
Device name : STM32WLxx
Flash size : 256 KBytes
Device type : MCU
Device CPU : Cortex-M4
UPLOADING OPTION BYTES DATA ...
Bank : 0x00
Address : 0x58004020
Size : 96 Bytes
██████████████████████████████████████████████████ 100%
Bank : 0x01
Address : 0x58004080
Size : 8 Bytes
██████████████████████████████████████████████████ 100%
OPTION BYTES BANK: 0
Read Out Protection:
RDP : 0xAA (Level 0, no protection)
BOR Level:
BOR_LEV : 0x0 (BOR Level 0 reset level threshold is around 1.7 V)
User Configuration:
nBOOT0 : 0x1 (nBOOT0=1)
nBOOT1 : 0x1 ()
nSWBOOT0 : 0x1 (BOOT0 taken from PH3/BOOT0 pin)
SRAM_RST : 0x1 (SRAM1 and SRAM2 are not erased when a system reset occurs)
SRAM2_PE : 0x1 (SRAM2 parity check disable)
nRST_STOP : 0x1 (No reset generated when entering the Stop mode)
nRST_STDBY : 0x1 (No reset generated when entering the Standby mode)
nRST_SHDW : 0x1 (No reset generated when entering the Shutdown mode)
WWDG_SW : 0x1 (Software window watchdog)
IWGD_STDBY : 0x1 (Independent watchdog counter running in Standby mode)
IWDG_STOP : 0x1 (Independent watchdog counter running in Stop mode)
IWDG_SW : 0x1 (Software independent watchdog)
BOOT_LOCK : 0x1 (CPU1 CM4 Boot lock enabled)
C2BOOT_LOCK : 0x1 (CPU2 CM0+ Boot lock enabled)
IPCCDBA : 0x3FFF (0x3FFF)
Security Configuration Option bytes ESE:
ESE : 0x1 (Security enabled)
PCROP Protection:
PCROP1A_STRT : 0xFF (0x803FC00)
PCROP1A_END : 0x0 (0x8000000)
PCROP_RDP : 0x1 (PCROP zone is erased when RDP is decreased)
PCROP1B_STRT : 0xFF (0x803FC00)
PCROP1B_END : 0x0 (0x8000000)
Write Protection:
WRP1A_STRT : 0x58 (0x802C000)
WRP1A_END : 0x7D (0x803E800)
WRP1B_STRT : 0x0 (0x8000000)
WRP1B_END : 0xA (0x8005000)
OPTION BYTES BANK: 1
Security Configuration Option bytes:
SFSA : 0x38 (0x38)
FSD : 0x0 (System and Flash secure. This bit can only be accessed when HDPADIS = 0)
DDS : 0x1 (CPU2 debug access disabled (when also enabled by C2SWDBGEN))
HDPSA : 0x7D (0x7D)
HDPAD : 0x0 (User Flash hide protection area access enabled.)
SUBGHSPISD : 0x1 (FSD=0 and SUBGHSPISD=1: SPI3 security disabled)
C2OPT : 0x1 (SBRV will address Flash memory, from start address 0x0800 0000 + SBRV.)
NBRSD : 0x1 (SRAM1 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0)
SNBRSA : 0x1F (0x1F)
BRSD : 0x0 (SRAM2 is secure if FSD=0 and non-secure otherwise. This bit can only be accessed when HDPADIS = 0)
SBRSA : 0x0 (0x0)
SBRV : 0xDA00 (0xDA00)
