Hi, I am working with a NUCLEO-WB15CC and can't erase all of the 320 KBytes Flash. When using the STM32_Programmer_CLI the following works perfectly fine:
STM32_Programmer_CLI.exe -c port=SWD -e [0 55]
but with
STM32_Programmer_CLI.exe -c port=SWD -e [0 56]
or any other value larger than 55 of the upper sector index, I get the error message
Error: Sector erase operation failed at least for one of the existing specified sectors
I already tried to reset the board to factory settings (as proposed in other posts) by
STM32_Programmer_CLI.exe -c port=SWD reset=HWrst -w32 0x5800040c 0x00008000
This didn't help and I'm running out of ideas. Any suggestions? Thanks in advance.
--
Enclosed is the output of the command to display the option bytes by
STM32_Programmer_CLI.exe -c port=SWD -ob displ
-------------------------------------------------------------------
STM32CubeProgrammer v2.12.0
-------------------------------------------------------------------
ST-LINK SN : 066EFF363946433043082412
ST-LINK FW : V2J37M27
Board : NUCLEO-WB15CC
Voltage : 3.28V
SWD freq : 4000 KHz
Connect mode: Normal
Reset mode : Software reset
Device ID : 0x494
Revision ID : Rev Z
Device name : STM32WB1xxx
Flash size : 320 KBytes
Device type : MCU
Device CPU : Cortex-M4
BL Version : 0xB1
UPLOADING OPTION BYTES DATA ...
Bank : 0x00
Address : 0x58004020
Size : 60 Bytes
Bank : 0x01
Address : 0x5800403c
Size : 4 Bytes
Bank : 0x02
Address : 0x58004080
Size : 8 Bytes
OPTION BYTES BANK: 0
Read Out Protection:
RDP : 0xAA (Level 0, no protection)
BOR Level:
BOR_LEV : 0x0 (BOR Level 0 reset level threshold is around 1.7 V)
User Configuration:
nBOOT0 : 0x1 (nBOOT0=1)
nBOOT1 : 0x1 (Boot from code area if BOOT0=0 otherwise system Flash)
nSWBOOT0 : 0x0 (BOOT0 taken from the option bit nBOOT0)
SRAM2RST : 0x1 (SRAM2 is not erased when a system reset occurs)
SRAM2PE : 0x1 (SRAM2 parity check disable)
nRST_STOP : 0x1 (No reset generated when entering the Stop mode)
nRST_STDBY : 0x1 (No reset generated when entering the Standby mode)
nRSTSHDW : 0x1 (No reset generated when entering the Shutdown mode)
WWDGSW : 0x1 (Software window watchdog)
IWDGSTDBY : 0x1 (Independent watchdog counter running in Standby mode)
IWDGSTOP : 0x1 (Independent watchdog counter running in Stop mode)
IWDGSW : 0x1 (Software independent watchdog)
GPIO_MODE_PB11: 0x1 (If RESET_MODE_PB11 = 0: Standard GPIO pad functionality, Only internal RESET possible. If RESET_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode), GPIO functionality is not available on PB11.)
RESET_MODE_PB11: 0x1 (If GPIO_MODE_PB11 = 0: Reset input only, a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin. If GPIO_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode).)
IRH : 0x1 (Internal resets drives NRST pin low until it is seen as low level.)
ESE:
ESE : 0x1 (Security enabled)
PCROP Protection:
PCROP1A_STRT : 0x1FF (0x807FC00)
PCROP1A_END : 0x0 (0x8000400)
PCROP_RDP : 0x0 (PCROP zone is kept when RDP is decreased)
PCROP1B_STRT : 0x1FF (0x807FC00)
PCROP1B_END : 0x0 (0x8000400)
Write Protection:
WRP1A_STRT : 0xFF (0x807F800)
WRP1A_END : 0x0 (0x8000000)
WRP1B_STRT : 0xFF (0x807F800)
WRP1B_END : 0x0 (0x8000000)
OPTION BYTES BANK: 1
IPCCDBA-AA:
IPCCDBA : 0x0 (0x20010000)
OPTION BYTES BANK: 2
Security Configuration Option bytes:
SFSA : 0x38 (0x801C000)
FSD : 0x0 (System and Flash secure)
DDS : 0x1 (CPU2 debug access disabled)
C2OPT : 0x1 (SBRV will address Flash)
BRSD_B : 0x0 (SRAM2b is secure)
SBRSA_B : 0x0 (0x20038000)
BRSD_A : 0x0 (SRAM2a is secure)
SBRSA_A : 0xA (0x20032800)
SBRV : 0x11800 (0x8000000)
