LPUART Clock Instability Causing Bit Errors on STM32WLE5 using LSE
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2025-04-01 4:51 AM - last edited on 2025-04-08 3:53 AM by KDJEM.1
Technical Description of LPUART Communication Error
Configuration:
- STM32WLE5 LPUART operating with LSE (Low Speed External) clock source
- Configured baud rate: 9600 bps
- To measure the TX signals, a minimal firmware created by CubeMX was used to rule out software problems.
Observed Issue: When receiving large data volumes (exceeding 300 bytes), occasional bit errors are occurring. To diagnose the problem, the TX signal was analyzed using an oscilloscope while repeatedly transmitting the pattern 0x55.
Oscilloscope Findings: Significant variations in bit timing were observed. The bit frequency varied from 8.173 kHz to 11.22 kHz, representing substantial deviation from the expected consistent timing for 9600 baud.
Analysis: Given that the datasheet specifies an expected error rate of only 0.1%, these timing variations are abnormal. Such significant timing inconsistencies in the transmit signal would likely cause corresponding reception errors, particularly with larger data transfers, as the timing drift accumulates.
Potential Causes:
- LSE oscillator instability can be excluded. Was measured with LSCO and have only a drift from +- 20 Hz
- Clock configuration issues
- Possible hardware limitations when using LSE as LPUART clock source which were not mentioned?
This level of clock instability (>30% variation) would definitely cause reception errors, as UART communication relies on precise timing between transmitter and receiver. If similar variations occur on RX, they would directly contribute to the observed bit errors.
Therefore I would be grateful for any help that can help me.
Andreas
- Labels:
-
STM32WL series
-
UART-USART
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2025-05-05 3:10 AM
Hello @APell.3
Could you please try to reproduce the behavior with a higher frequency (maybe changing the clock source of the LPUART. I think what you are seeing is the same behavior descripted on the errata 2.9.1 of the ES0506 Rev5.
Best Regards.
STTwo-32
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