I'm running the IEE802.5.4 protocol stack on the STM32WB50. Why does the System Clock Mtu source switch on its own?

[MNitt.1]

Hello

We are verifying the communication of the IEEE802.15.4 protocol stack with STM32WB50. I tried to insert a 1ms interrupt on CPU1, but when I initialized and enabled IEEE802.15.4, the 1ms interrupt was extended to 2ms. The cause was that the System Clock Mtu input was switched from PLLCLK to HSE_SYS.

The external clock 32MHz is put in the HSE, and the system clock is set to 64MHz by the PLL. And I set the source of System Clock Mtu to PLLCLK.

Please tell me why it switches.

Can the Systemu Clock Mtu source be fixed to PLLCLK?

[MNitt.1]

This is the sequel.

After tracking, the SWS / SW of the RCC clock configuration register (RCC_CFGR) changed from 11: PLL selected as system clock to 10: HSE selected as system clock after LL_C1_IPCC_SetFlag_CHx () was called.

I couldn't find such a description in any of the materials.

Why is this happening?