2023-11-02 12:58 AM
Hi,
is there an error in the datasheet? The data seems counterintuitive:
FT pin input leakage current (max.) is
- 150 nA for 0 to VDD
-2500 nA for VDD to VDD+1V
-250 nA for VDD+1V to 5,5V
Shouldn´t the last value be in uA perhaps?
Kind regards
René
Solved! Go to Solution.
2023-11-07 06:05 AM
There is no error. it is indeed nA as unit.
The reason of a higher leakage when VDD is in the window VDD max -> VDD max + 1V is the mechanism managing the 5V tolerance of the pin. This mechanism is less optimized in this window than in the window VDD max +1V -> 5.5V where all transistors ensuring the 5V tolerance are well biased, thus generating a lower leakage.
2023-11-02 02:52 AM
Hello @RWeil.2,
I'm checking this internally, I will get back to you.
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2023-11-07 06:05 AM
There is no error. it is indeed nA as unit.
The reason of a higher leakage when VDD is in the window VDD max -> VDD max + 1V is the mechanism managing the 5V tolerance of the pin. This mechanism is less optimized in this window than in the window VDD max +1V -> 5.5V where all transistors ensuring the 5V tolerance are well biased, thus generating a lower leakage.
2023-11-08 11:15 PM
Thank you for the clarification!