STM32F7 DCMI support for output mode?

[arne]

Posted on July 02, 2015 at 12:21

Reading the reference manual RM0385 (DocID026670 Rev 1) in the introduction to the DCMI on p. 478 I encountered this:

''[...] This interface is also able to transmit a parallel data flow, allowing it to emulate a camera module interfacing with another camera interface. It may also be used as a generic synchronous parallel inteface ensuring a high data rate transfer, in receive or in transmit mode.[...]'' However, I find no mention of the transmit mode in the remainder of the chapter. Can someone please clarify? #stm32f7 #dcmi

[Amel NASRI]

Posted on July 10, 2015 at 13:10

Hello krueger.arne,

The STM32F7 DCMI doesn't support the output mode.So, we shouldn't speak about transmission for DCMI interface.This will be fixed in next revision of RM085.Thanks for reporting this error.-Mayla-

[MasterT]

Hi,

I see, that RM0385 is fixed now.

I have the same confusion with stm32F446, doc. RM0390:

"This interface is also able to transmit a parallel data flow, allowing it to emulate a camera module interfacing with another camera interface."

Paragraph 15.1, page 423.

My understanding, that is also misleading info and should be corrected as well.

[Tesla DeLorean]

It's a pity, because you'd have thought that would have been useful functionality.

For output you can drive GPIO (BSRR) from a pattern buffer via TIM+DMA(2)

[MasterT]

Right, I already write a code to drive GPIOC over DMA2.

The problem I encountered, is that DMA is loosing some data when it's running at high speed - 36 MHz, having data rate 36 MBytes /sec. Since GPIO port doesn't have DMA underrun /overrun hardware functionality, I can't find a way to accelerate speed at that level, basically glitches start appear at about 12.8 MBytes/sec. In overall datarate isn't much higher than stm32f1xx or stm32f3xx running at 72 MHz (stm32f446 has 180 MHz internal clock).

[Tesla DeLorean]

Yeah, getting a bit high in speed there, bandwidth and contention becoming dominant issues. Also jitter in signal placement.

At some point a FPGA/CPLD would be more appropriate.

The FMC/FSMC external bus would be a better route than GPIO.

[Amel NASRI]

Hi @MasterT​ ,

The last 2 sentences should be removed from the introduction of DCMI chapter in RM0390.

This is tracked internally, thanks for highlighting the error.

-Amel