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Minimum space between frame buffers

TDele.1
Associate III

Hello everyone,

I'm currently developing a project using Touchgfx on a custom board with a STM32F469II, external RAM/FLASH, SD card and a 1024x600 screen.

I'm having trouble placing the frame buffer in the external RAM close to eachover. Right now, the following configuration in the "TouchGFXHAL.cpp" is working quite well:

setFrameBufferStartAddresses((void*)0xC0000000, (void*)0xC0200000, (void*)0xC0400000);

The parameters are as follow:

- The first address is the start of the first frame buffer.

- The second address is the start of the second frame buffer (use for multi-buffering).

- The third address is the start of the animation storage space (use for slide transition between screen).

All of them are placed in the external RAM space of the custom board which goes from 0xC0000000 to 0xC07FFFFF (8 MB).

With that, a fourth and final space is added which is the dynamic bitmap cache which stores images from the SD card to be displayed over the screen with TouchGFX.

Howerver, when I want to maximize that fourth space to get as much place as possible to store images from the SD card (as an example, backgrounds which take a lot of space), I'm having a lot of trouble decreasing the space between the framebuffers, here's what I've found out so far:

  • I have no trouble downloading pictures from the SD card into the cache once it is setup.

  • In theory, each frame buffer should take exactly (1024*600*16)/8 = 0x12C000 in my configuration in RGB565 meaning that I should be able to setup the frame buffers like so : setFrameBufferStartAddresses((void*)0xC0000000, (void*)0xC012C000, (void*)0xC0258000); with 0x47C000 space to spare for the bitmap cache storage.

  • I have no problem setting the 3rd framebuffer to its minimal size meaning that the bitmap cache can start at 0xC052C000 with a size of 0x2D4000.

  • However, as soon as I decrease the space between any other framebuffer (even one byte), the image on the screen starts to jitters and sometimes shakes randomly when the image on the screen is static and a lot more when performing a transition (any of them).

  • The more I limit the space between framebuffers, the more this shaking seem to be greater (not 100% sure about that one).

  • Removing the second and/or third framebuffer doesn't change anything (the image is still shaking).

  • Changing the LTDC parameters (porch, synch, ...) does not seem to solve the issue but only moves the picture area on the screen.

  • When debugging, If I go watch the memory occupied by each framebuffer, I can indeed see that there is no data where there should not be (i.e. for the first frame buffer, the screen's pixels stop at 0xC012C000 as expected and there is no data until the next frame buffer at 0xC0200000).

  • Changing the type or the speed of the transition does not solve the issue.

I'v already contacted the screen manufacturer which told me that it could be dut to the fact that DMA2D can be configured to 8/16/32 -bit access and a wrong alignement could explain the jitters. However, since he's not quite sure how to check the DMA2D access size and if it's really what's causing the shaking, I'm asking here if anyone ever experienced that issue and if so how to fix this problem.

Thanks in advance,

DELETRAZ Tristan

1 ACCEPTED SOLUTION

Accepted Solutions
MM..1
Chief II

You need read LTDC appnotes , and FYI LTDC need that framebuffer start address meet some conditions. For example cant **** by one byte or word...

Second condition is FMC SDRAM access on banks and optimal is every buffer on separated bank. On your SDRAM maybe one bank is 2M and have four.

When you need you can only go down with framerate aka dotclock and then LTDC and FMC can cooperate with other address , but this need meet basic condition, for example must be multiply of 64...

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2 REPLIES 2
MM..1
Chief II

You need read LTDC appnotes , and FYI LTDC need that framebuffer start address meet some conditions. For example cant **** by one byte or word...

Second condition is FMC SDRAM access on banks and optimal is every buffer on separated bank. On your SDRAM maybe one bank is 2M and have four.

When you need you can only go down with framerate aka dotclock and then LTDC and FMC can cooperate with other address , but this need meet basic condition, for example must be multiply of 64...

TDele.1
Associate III

Thanks a lot for the anwser. I didn't know about the condition where the frame buffers should be in different banks.

Tristan