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How many pixels can STM32F429xx LTDC support?

许和平
Associate II

In STM32F429ZI datasheet (DocID024030 Rev 10), in the beginning (page 1) it says:"LCD-TFT controller with fully programmable resolution (total width up to 4096 pixels, total height up to 2048 lines and pixel clock up to 83 MHz)". But in functional overview LTDC chapter (page 24) and STM32F4 reference manual (RM0090 Rev 19) LTDC chapter (page 480), they say  LTDC support resolution can only up to XGA (1024x768) resolution. Which one shall I believe, 4096x2048 or 1024x768?

By the way, what is XGA​ resolution? Does it simply means 1024x768 pixels? If a LCD says it supports XGA resolution, does it mean this LCD has 1024x768 pixels?

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Accepted Solutions
KDJEM.1
ST Employee

Hello @和平 许​ ,

First let me thank you for posting.

The LTDC peripheral allows the user to interface with any display size with total width of up to 4096 pixels and total height of up to 2048 lines.

The LTDC peripheral can support any display size that respects the maximal programmable timing parameters in the registers and the maximal supported pixel clock.

For more explanation, I advise you to refer to AN4861 LCD-TFT display controller (LTDC) on STM32 MCUs and precisely Fully programmable timings for different display sizes Section.

The XGA resolution is 1024x768.

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

3 REPLIES 3
KDJEM.1
ST Employee

Hello @和平 许​ ,

First let me thank you for posting.

The LTDC peripheral allows the user to interface with any display size with total width of up to 4096 pixels and total height of up to 2048 lines.

The LTDC peripheral can support any display size that respects the maximal programmable timing parameters in the registers and the maximal supported pixel clock.

For more explanation, I advise you to refer to AN4861 LCD-TFT display controller (LTDC) on STM32 MCUs and precisely Fully programmable timings for different display sizes Section.

The XGA resolution is 1024x768.

When your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Kaouthar

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

MM..1
Chief

You mix not real questions. Little match

Refresh 60HZ 4096x2048 require pixel clock over 500MHz == not real

6HZ refresh ... 50MHz DCLK == maybe ,but normal displays is on 6Hz unusable

,but if your display 4096x2048 have own framebuff and internal refresh rate , you can use it

It has to meet all the rules, so the subset of workable values will tend to be a lot smaller.

The width and height limited by the related counter sizes.

As the screen expands you tend to run out of bandwidth.

1024x768 16bpp 60 Hz -> 48 MHz

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