Hi!
I have a board with a STM32H730 chip, my RAM is configured as not cacheable and instruction access disabled,as performance decreases a lot otherwise, but now i'm getting a hardfault after drawCachedAreas(); is executed,
As i can't see what that function is doing, i thought that mayb someone could help me.
If someone is invested enough here is my MPU config
void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct;
/* 1) Deshabilita el MPU para reconfigurar */
HAL_MPU_Disable();
/* ————————————————————————————————————————————————————
* Región 0: fondo 4 GB NO_ACCESS (cubre todo excepto QSPI, SDRAM y SRAM)
*———————————————————————————————————————————————————*/
MPU_InitStruct = (MPU_Region_InitTypeDef){0};
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.BaseAddress = 0x00000000U;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.SubRegionDisable = 0x87; // deja libres subregs 2 y 3
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* ————————————————————————————————————————————————————
* Región 1: QSPI externa @0x9000_0000, 64 MB (XIP)
*———————————————————————————————————————————————————*/
MPU_InitStruct = (MPU_Region_InitTypeDef){0};
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER1;
MPU_InitStruct.BaseAddress = 0x90000000U;
MPU_InitStruct.Size = MPU_REGION_SIZE_64MB;
MPU_InitStruct.SubRegionDisable = 0x0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1; // normal, cacheable
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; // XIP
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* ————————————————————————————————————————————————————
* Región 2: SDRAM externa @0x7000_0000, 8 MB <— toda la RAM externa
* • non-cacheable (evita incoherencias LTDC/DMA)
* • non-bufferable (hace el bus más “estricto” pero es el estado original)
* • shareable (mantiene coherencia para masters DMA)
*———————————————————————————————————————————————————*/
MPU_InitStruct = (MPU_Region_InitTypeDef){0};
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER2;
MPU_InitStruct.BaseAddress = 0x70000000U;
MPU_InitStruct.Size = MPU_REGION_SIZE_8MB;
MPU_InitStruct.SubRegionDisable = 0x0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* ————————————————————————————————————————————————————
* Región 3: AXI-SRAM interna @0x2400_0000, 512 KB
* • cacheable + bufferable para código/variables críticas
*———————————————————————————————————————————————————*/
MPU_InitStruct = (MPU_Region_InitTypeDef){0};
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER3;
MPU_InitStruct.BaseAddress = 0x24000000U;
MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
MPU_InitStruct.SubRegionDisable = 0x0;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* 2) Reactiva el MPU con “privileged default map” para todo lo que no cubran
las regiones anteriores */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}Base addresses are all like in the linker file, except flash that starts at 0x90000200
**EDIT**
I forgot to mention, in the MPU config if i set RAM as cacheable, the hardFault dissapears, but i need it to be not cacheable or i get like 10 times worse performance.
