AN4861 Table 10 meaning.

[CScha.2]

I am looking at the maximal supported pixel clock of the stm32F4x9 with SDRAM 32bit. The pixel rate for 640x320 pixels at 60hz refresh is 640*480*60 = 18432000. There is a table in AN4861 Table 10 that states the maximal supported pixel clock is 35Mhz with 1 layer 32 bpp. What exactly is this refering to ? If I take 18432000*32 = 589824000. Is the table 10 referirng to the transfer speed from the SDRAM ? Do I take this number and mulitply it by 32 or 35mhz * 32 to get the actually throughput for this device ?

[waclawek.jan]

> The pixel rate for 640x320 pixels at 60hz refresh is 640*480*60 = 18432000

[emphasis mine]

Why? Typo?

Note, that you'd need somewhat higher pixel clock to account for the blanking intervals, so you'd need around 20MHz (how much exactly depends on the display).

> If I take 18432000*32 = 589824000.

Why would you do that. One pixel is 32-bit and the whole path (except actual data to the display) is 32-bit wide.

The 35MHz value in table 10 means, that you could go up to cca 35MHz/20MHz*60Hz=105Hz frame refresh rate before the LTDC controller ceasing to be able to read out pixel data fast enough.

Or, if you look at the 2-layers value which for 32/32 bpp is 18MHz < 20MHz, i.e. you can't use two 32/32 layers at 60Hz frame rate.

JW

[CScha.2]

OK. That is what I wanted to know. The max pixel rate is greater than 640*480*60, Correct ? I wanted to make sure that the did not mean I had to take the 32 bit bus in to account even though that made no sense to me. I now understand my two layer limitations as well. Thanks for the help. You can close the case.

[waclawek.jan]

> The max pixel rate is greater than 640*480*60, Correct ?

That is, assuming some reasonable settings for the SDRAM (maybe characterized in the same AN, I don't know, I don't use LTDC) and assuming you won't use SDRAM for anything other than the video data.

JW