I've been just bitten by https://community.st.com/s/feed/0D50X00009XkW6NSAV . [reconstructed]
In an already proven working piece of code, I first check if an array's first word is equal to a constant (signature), then I reset the CRC and then feed it in a for loop by that array (including its first word, i.e. the signature). A newer version of gcc optimized this more aggressively than previous gcc version, and as from the signature test it "knew" that the first word of array is equal to a constant (which it already held in a register), it generated a write from that register immediately after the write to CRC reset, and only after that fed the remainder of the array in the loop.
I've checked RM0090 which is currently in version 18, and there's still no mention that I'd have to wait until the reset bit gets autocleared, or any specified time after writing the reset.
ST, can this please be specified.
Also, isn't the same problem present in other STM32 models?
JW
