Working with TIM Output Compare

[Maxim Petrenko]

Posted on June 16, 2018 at 23:08

I try to generate pulses for the stepping motor at the Output Compare output.

The time between their leading fronts varies (acceleration / deceleration).The control of delays based on the well-known principle: free run 16-bit timebase counter with modulus of 65536.The delay is formed by updating the CC register, adding the delay duration to the previous CC value.Two CC channels are used, operating with a fixed time shift.First, CC2 is triggered; its interrupt performs calculations and check conditions to make a step.Then CC1 is triggered to form the front of the step pulse, if needed.CC3 and CC4 channels are reserved for second stepping motor but not used.

However, I can not start these interrupts in the required sequence.

Now I'm stuck with the fact that approximately once per timebase cycle (~ 65 mc), interrupt flags CC3 and CC4 are setting, for which CC events and interrupt request generation are disabled during initialisation and never enable in main loop.It seems that the timebase Update event re-enables CC events and CC interrupt reqiests, but such behavior does not correspond to datasheet.

Below is a picture from the analyzer and the text of the interrupt handler.

void TIM3_IRQHandler(void){ /* USER CODE BEGIN TIM3_IRQn 0 */ if (LL_TIM_IsActiveFlag_CC1(TIM3)) // STEP1 pulse starts { LL_TIM_ClearFlag_CC1(TIM3); sm_driver_PostStepA(); } if (LL_TIM_IsActiveFlag_CC2(TIM3)) // STEP1 prepare { LL_TIM_ClearFlag_CC2(TIM3); speed_cntr_PreStep(0); // This function calls Cannel1 test pulses (throwgh GPIO) with proper timing } if (LL_TIM_IsActiveFlag_CC3(TIM3)) // This flag setting is disabled and never enable! { LL_TIM_ClearFlag_CC3(TIM3); //++++++++++++++++++++++++++++ // Cannel1 test pulses; don't undestand why it appears in timing! HAL_GPIO_WritePin(StpMotor2_Current_GPIO_Port,StpMotor2_Current_Pin,GPIO_PIN_SET); HAL_GPIO_WritePin(StpMotor2_Current_GPIO_Port,StpMotor2_Current_Pin,GPIO_PIN_RESET); //++++++++++++++++++++++++++++ // sm_driver_PostStepB(); } if (LL_TIM_IsActiveFlag_CC4(TIM3)) // This flag setting is disabled and never enable! { LL_TIM_ClearFlag_CC4(TIM3); // speed_cntr_PreStep(1); // But in fact program reaches this point! } }#general-purpose-timers

[waclawek.jan]

Posted on June 16, 2018 at 23:44

Now I'm stuck with the fact that approximately once per timebase cycle (~ 65 mc), interrupt flags CC3 and CC4 are setting,

That's expected - they are set when CCRx == CNT, which, if you don't change CCRx to beyond ARR, occurs once every timebase cycle.

They don't trigger an interrupt though, if they are not enabled by the corresponding bits in DIER.

You simply should not check them in the ISR.

JW