Why are 32 bits timers longer to be set up with pwm mode using DMA burst feature? (F446RE)

[YSall.1]

Hi,

I am using this code, TIM1,3,4,8 are working directly like a charm, but TIM2 and TIM5 the only 32 bits timers are taking approximately 1 minute and 45 seconds to be working. Does anyone know where comes this issue?

  uint16_t buffer1[12] = {0,35,0, 18,2, 56,0,15,2,45,0,12};
  uint32_t buffer2[12] = {0,180000000,0, 90000000,2, 56,0,15,2,45,0,12};
  uint16_t buffer3[12] = {0,35,0, 18,2, 56,0,15,2,45,0,12};
  uint16_t buffer4[12] = {0,35,0, 18,2, 56,0,15,2,45,0,12};
  uint32_t buffer5[12] = {0,35,0, 18,2, 56,0,15,2,45,0,12};
  uint16_t buffer8[12] = {0,35,0, 18,2, 56,0,15,2,45,0,12};
 
 
  HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1); //fonctionne
  HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1); //fonctionne
  HAL_TIM_PWM_Start(&htim3, TIM_CHANNEL_1); //fonctionne
  HAL_TIM_PWM_Start(&htim4, TIM_CHANNEL_1); //fonctionne
  HAL_TIM_PWM_Start(&htim5, TIM_CHANNEL_1); //fonctionne
  HAL_TIM_PWM_Start(&htim8, TIM_CHANNEL_1); //fonctionne
 
  HAL_TIM_DMABurst_MultiWriteStart(&htim1, TIM_DMABASE_PSC, TIM_DMA_UPDATE, (uint32_t*) buffer1, TIM_DMABURSTLENGTH_4TRANSFERS,12);
  HAL_TIM_DMABurst_MultiWriteStart(&htim2, TIM_DMABASE_PSC, TIM_DMA_UPDATE, (uint32_t*) buffer2, TIM_DMABURSTLENGTH_4TRANSFERS,12);
  HAL_TIM_DMABurst_MultiWriteStart(&htim3, TIM_DMABASE_PSC, TIM_DMA_UPDATE, (uint32_t*) buffer3, TIM_DMABURSTLENGTH_4TRANSFERS,12);
  HAL_TIM_DMABurst_MultiWriteStart(&htim4, TIM_DMABASE_PSC, TIM_DMA_UPDATE, (uint32_t*) buffer4, TIM_DMABURSTLENGTH_4TRANSFERS,12);
  HAL_TIM_DMABurst_MultiWriteStart(&htim5, TIM_DMABASE_PSC, TIM_DMA_UPDATE, (uint32_t*) buffer5, TIM_DMABURSTLENGTH_4TRANSFERS,12);
  HAL_TIM_DMABurst_MultiWriteStart(&htim8, TIM_DMABASE_PSC, TIM_DMA_UPDATE, (uint32_t*) buffer8, TIM_DMABURSTLENGTH_4TRANSFERS,12);

[waclawek.jan · Accepted solution]

Since DMA is triggered by update, if you did not set ARR to some smaller value, the first DMA transfer occurs after the first Update (i.e. timer overflow), and in 32-bit timers, it's after 0xFFFF'FFFF cycles. If ARR preload is enabled (by setting TIMx_CR1.ARPE), then it takes another full cycle of the timer until the first value written by DMA to ARR gets active.

JW

[YSall.1]

Thank you for your response!