Which memory can be used for periph to mem transfer?

[Gunnar Bohlen]

Posted on June 23, 2017 at 16:05

Hello,

I use the CPU STM32F765.

I want to use DMA2 to transfer ADC-results into memory.

This works fine if I use DTCM-Memory for the destination  (128kbyte  from 0x20000000 to 0x2001ffff)

If I use SRAM1, DMA seems to work (I get transfer complete interrupt, ADC registers indicate that adc-values were read), but no data is in the programmed addresses.

Is it possible that ADC to DMA transfer only works when DTCM memory is used  for the destination?

Some time ago I maybe had a similar problem: I use Keil Middleware to implement a file system using an SD-card. It started to work after I told the middleware to use memory buffers at 0x20000000.

In the reference manual I read about DMA that it can address the complete memory range.

If it is required to specify DTCM memory for peripheral to memory transfers: where is this documented?

If SRAM1 should also work: What could be the reason why DMA works with DTCM, but not with SRAM1?

Thank you.

[waclawek.jan · Accepted solution]

Posted on June 23, 2017 at 20:23

If SRAM1 is cached, the processor may see values from cache instead of values written newly by the DMA.

You may want to read AN4839.

JW

[Gunnar Bohlen]

Posted on June 26, 2017 at 09:09

Thanks a lot.

In the AN4839 I read:

>Another case is when the DMA is writing to the SRAM1 and the CPU is going to read data

>from the SRAM1. To ensure the data coherency between the cache and the SRAM1, the

>software must perform a cache invalidate before reading the updated data from the SRAM1.

This is exactly my case (ADC data transfered to SRAM1 via DMA2)

Does this mean I cannot use the MPU to configure a small range of SRAM1 so that I can use it for DMA-Write and CPU-Read without invalidating the cache manually?

GB

[waclawek.jan]

Posted on June 26, 2017 at 10:41

Does this mean I cannot use the MPU to configure a small range of SRAM1 so that I can use it for DMA-Write and CPU-Read without invalidating the cache manually?

The AN is not crystal clear. IMO you can. One of the obstacles may the limited number of regions (8 in those 'F7 I looked at) in the MPU, but that is usually enough for all practical applications with a bit of planning.

JW