2021-10-31 08:36 PM
Hi Everyone,
I found the document(AN5354) talk about 16bits ADC Max sampling Rate and I verify that on M7 Core. It's correct.
My implement include Total 3 ADC 3 Channel(one channel per one ADC) run 1Mhz Sampling rate and using DMA with timer trigger
But I implement the same ADC configuration on M4 core, i can't generate the max sampling rate as document. It has been slower than expected
The M4 core should be slower than M7 right?
If so, Dose anyone know how slow and the max sampling rate on M4 core ?
2021-11-01 06:29 AM
The peripherals are separate from the cores. The max speed should be independent of the core you're using to configure it.