What is the meaning of "data read width " in the flash memory bank organisation of STM32 MCU?

SSRIN.1 · ‎2021-09-02

I was going through embedded flash programming documentation of STM32F7 . I came across a term called "data read width". can some one explain this term ?

Flash memory single bank organization (256 bits read width)

Flash memory dual bank organization (128 bits read width)

waclawek.jan · ‎2021-09-02

FLASH memories are relatively slow (their access time is cca 30-50ns, that's why there are waitstates involved if system clock is higher than 20-30MHz). There are several ways how to mitigate this; one is to read in parallel several words at once. This is the data read width, i.e. the FLASH is organized so that 128/256 bits are read at once, and then the FLASH interface supplies them to rest of the system in 32/64-bit chunks. This speeds things up if several words have to be read consecutively, which is the typical case for code execution (which is in turn the typical application for FLASH).

JW

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waclawek.jan · ‎2021-09-02

FLASH memories are relatively slow (their access time is cca 30-50ns, that's why there are waitstates involved if system clock is higher than 20-30MHz). There are several ways how to mitigate this; one is to read in parallel several words at once. This is the data read width, i.e. the FLASH is organized so that 128/256 bits are read at once, and then the FLASH interface supplies them to rest of the system in 32/64-bit chunks. This speeds things up if several words have to be read consecutively, which is the typical case for code execution (which is in turn the typical application for FLASH).

JW