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Debug infrastructure in STM32F7

Associate III

For a long time I have been trying to guess how debug components are connected to the Cortex-M7 core in STM32F7 series of microcontrollers. It is supposed to be shown in e.g. the document RM0410 in Figure 587. This figure seems to be a copy of the same drawing from the documentation of a microcontroller based on the Cortex-M4 processor (e.g. Figure 403 from the document RM0316). However, the internal architecture of the Cortex-M7 and Cortex-M4 processors is different, so Figure 587 in RM0410 appears to be incorrect. This is indicated by, for example, Figure 859 in RM0399, which shows that the AHB-AP port is attached differently to the Cortex-M7 and Cortex-M4 processors. So, could anyone confirm or deny my assumptions?