What is primary risk for STM32F427 ADC if VDDA-VREF+ exceeds 1.2V max recommended operating difference by 300mv. Our system VDD=3.3V, VDDA=3.3V, VREF+=1.8V, Accuracy lost? IC damage?

[JEsko]

DocID024030 Rev 9 states:

4. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.

Normally, I would just make changes to satisfy, but a change at present product development stage is very costly. Using LQFP144 pkg if that matters.

[waclawek.jan]

I'm afraid you won't receive the sort of answer you'd like to, here. This here is primarily a user-driven forum with casual ST presence. You want to talk to a ST representative, or a FAE. But, unless you represent some $M+ buying power, I'm afraid ST won't rush to answer this sort of questions, and you're left with the "costly change at this development stage" option (and changes are quite high that you'd be left with that option anyway).

And, there's that ST's "ask a question" thingy on instagram https://www.instagram.com/p/BtiVoQFDtaN/ - related to EW in Nurnberg - you could ask also there, for the heck of it...

JW