2015-07-20 02:02 AM
In the
http://www.st.com/web/en/resource/technical/document/application_note/DM00115714.pdf
is written: ...During the startup phase VDDA must arrive first and be greater than or equal to VDD.
... Why that what if it is not so? Is it possible to start first VDD before VDDA? If yes, under which conditions?2015-07-20 10:22 AM
What time constraint? I said I liked 100ms. The STM32F4 POR has a minimum ~20us pulse width. I think that's a bit tight for sloppy external RC reset circuits, or supplies with ridiculous rise times between 1.2 and 2.7 V.
I suspect the 300mV comes from the fact there will be some internal conduction paths. Things aren't supposed to be powered that way, but might find a path, whether it's through internal or external parts.I'm not sure you're going to get ST engineers with familiarity of the silicon at this level answering on the forum.2015-07-20 10:52 AM
I mean a time constraint: VDDA must be before VDD by power on/off.