Using STM32F446xx TIM2, how to measure frequency > 1Mhz.

[Invn Invn]

Posted on March 06, 2017 at 23:45

Hello All, I am using STM32F446xx TIM2 to measure frequency > 1Mhz. I have set TIM2 to external clock and see the counter increment at every rising edge. I am reading this counter value in main function for test. But for highter frequencies over 200Khz to 5Mhz, how do I make this counter data pushed out so I can accurately measure frequency ?

[T J]

Posted on March 07, 2017 at 13:55

I would try to use the input capture function

set the input filter to Zero (if there is no noise on the digital input).

on the first inputcapture interrupt, save the timer value to last time

on the next inputcapture interrupt subtract the current timer value from the last and flag the foreground to calculate the frequency, and save the current timer value to last again.

if you have a 90Mhz clock source with no prescalers you will get rough figures.

to be more accurate;

if you can track the timer overflow count, and append to to the timer count..

then count 100 inputcapture events, then subtract the first timer value from the 100'th timer value, then you will have very good accuracy.

[Invn Invn]

Posted on March 07, 2017 at 17:22

I have tried input capture first but it doesn't work for frequency higher than 100khz as I think call back function itself must be taking several clock cycle and then reading from compare reg is additional .

Now I have set up for external clock so the counter increments at rising edge . So now I want to figure out how to get counter values our for an known interval.

Thanks Inv

[waclawek.jan]

Posted on March 07, 2017 at 17:51

OK so you have TIM2 set to external trigger, ARR set to as much as it gets.

Choose a second timer so that it can be a TRGI source for TIM2, look at the table in RM after TIMx_SMCR description. Say you've chosen TIM3. Set one of TIM3's CC channels, say CH1, in output compare mode to provide a pulse of a given length, say 1s (or less, depending on your needs for precision), using PWM1 mode, so that there's a falling edge of OCRef upon compare, ie. in the moment when interrupt is fired from it. Enable that interrupt in TIM3_DIER. Set TIM3 ARR so that after that 1s remains enough time for the ISR to comfortably read out TIM2 and reset its CNT. Set TIM3's CH1 output compare as TRGO. Set TIM2 in SMCR so that it's slave TRGI to be sourced from TIM3, and select gated mode. In the TIM3_CH1 ISR, read out TIM2_CNT and reset it.

Simpl'n'easy, isn't it.

JW

[Tesla DeLorean]

Posted on March 07, 2017 at 19:39

Not sure why an External Count mode would need to interrupt >100 KHz, or frankly at all. If you want accurate count per second you could trigger another TIM to DMA content of TIMx->CNT periodically, or read at 1KHz SysTick, and just delta the measurement over the integration period.

[T J]

Posted on March 07, 2017 at 23:41

Waclawek.Jan

That is an excellent suggestion.

totally seamless hardware functionality with very slight foreground requirements.

Turvey.Clive.002

also an excellent suggestion, again much less interrupts, again much better for stability.

Both of these suggestions are better than my suggestion, there is no doubt.