Use of VREFBUF on the STM32H753.

[JMall]

The voltage reference buffer (VREFBUF) seems to control what happens with the Vref+ pin, as described in this from the Reference Manual:

Table 225. VREF buffer modes

ENVR HIZ VREF buffer configuration

0 0

VREFBUF buffer OFF:

– VREF+ pin pulled-down to VSSA

0 1

External voltage reference mode (default value):

– VREFBUF buffer OFF

– VREF+ pin input mode

1 0

Internal voltage reference mode:

– VREFBUF buffer ON

– VREF+ pin connected to VREFBUF buffer output

1 1

Hold mode:

– VREFBUF buffer OFF

– VREF+ pin floating. The voltage is held with the external capacitor

– VRR detection disabled and VRR bit keeps last state

This says that 0,1 is the default (which is what I want), but when I read those bits they are always 0,0 -- even just after I've tried setting HIZ with:

HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE);

And a setting of 0,0 is supposed to pull the Vref+ pin down to Vssa, which really doesn't seem to be what it's doing.

My question is basically how this all really works?

Thanks.

[DShar.17]

Ah, good question - no it did not. This implyies that the peripheral was behaving as advertised (initialized to default state), but we just couldn't tell ... without the RCC enabling it, communication with it was disabled. But now I can change the pin state: with HIZ disabled, the voltage drooped way more.

[DShar.17]

there's even a handy __HAL_RCC_VREF_CLK_ENABLE() call