Updating the timer pwm frequency...

[magas09]

Posted on May 25, 2015 at 12:53

Hi!

I have one question: why when I update the timer PSC, ARR and CCR1 registers to change the frequency of PWM signal, the first pulse is generated with the earlier frequency and only second and next have desired frequency...?Should be done some reset operation, before updating the values of registers...?Thanks a lot... #stm32f4 #discovery #timers

[waclawek.jan]

Posted on May 25, 2015 at 13:09

Look at the figure at the beginning of the timer chapter in RM. See the shadows below some of the registers? Those registers may not be written directly, rather, you write read a shadow register. The condition the new value is copied to the working register upon an Update Event (roughly speaking counter overflow, read the whole timer chapter for the painful details); but it may depend on additional settings (see TIMx_CR1.ARPE and TIMx_CCMRy.OCzPE, and more with the Advanced timers (TIM1, TIM8)).

JW

[magas09]

Posted on May 25, 2015 at 13:41

How can we be get rid of this...? Is there some way or it is just a beauty of uC's and ''digital world''...?

[waclawek.jan]

Posted on May 25, 2015 at 14:00

Get rid of what?

I've given you the flags to switch on/off ''preload'' (i.e. shadowing) of most of the registers. ''Preload'' of prescaler (TIMx_PSC) can't be switched off; if you can't live with it and need prescaler with modified content, use a different timer as a prescaler and chain the timers. JW

[magas09]

Posted on May 25, 2015 at 14:54

I am really sorry about my low knowledge of uC... I am a beginner with only a half year experience...

Thanks a lot for your reply, I've found it in RM:''You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.''As I know it is done by those instructions:TIM_ARRPreloadConfig(TIM10, ENABLE);TIM_OC2PreloadConfig(TIM10, TIM_OCPreload_Enable) ;I have had those lines in my configuration file for timer but it isn't enough... Should I set this flags before each change of ARR value...?

[waclawek.jan]

Posted on May 25, 2015 at 15:04

''Preload'' in ST lingo means ''use the shadow, don't write directly to working register''. So, you probably want to *disable* the preloads...

JW

[magas09]

Posted on May 25, 2015 at 15:17

You had right... 

But I disabled:      TIM_OC1PreloadConfig(TIM10, TIM_OCPreload_Disable) ;     TIM_ARRPreloadConfig(TIM10, DISABLE);And the first period is also with the earlier settings... Any idea why it still hapens...?I have found those lines in RM:As the preload registers are transferred to the shadow registers only when an update eventoccurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register.But don't know if setting the UG bit in TIMx_EGR resolve the problem of first pulse...