Posted on June 27, 2014 at 09:18The crux of the problem is you have no real visibility into the internals of the usart, or the state of the counters/prescalers etc, or how it adjusts to the bit centre of received data. You can't really control when you are writing into the registers with respect to these things, and the behaviour therefore is going to be somewhat indeterminate. A gate level description of the implementation is unlikely to be forth coming.
On the receive side your most opportune time would be as RXNE is raised, marking that you are currently in whatever inter-symbol gap you have, ie stop bit(s) of last character vs start bit of next/current character. TXE will transition low-to-high at roughly the point it's going to output the start bit of the character it just moved from the holding register to the shift register.
You'll have to experiment. Put a scope or logic analyzer on the system and review what it does. Have GPIO reflect the state of RXNE, TXE either directly, or toggling as interesting transition points.
If I understood a little more about why this was all necessary, I could perhaps make some other suggestions.
