Unsuccessful entering in sleep mode and wait for interrupt for wakeup

[danesh]

Posted on December 10, 2015 at 14:50

Dear all,

I am using a STM32F103VEH micro-processor. I intend to put the processor into sleep mode and configure it so it will wake up by receiving any interrupt. I use the following code:   uint32_t tmpreg = 0;   tmpreg = PWR->CR;   tmpreg &= CR_DS_MASK;   tmpreg |= PWR_Regulator_LowPower;   PWR->CR = tmpreg;   // Ask the processor to sleep now.   SCB->SCR &= ~(SCB_SCR_SLEEPONEXIT | SCB_SCR_SLEEPDEEP);   // Wait for any interrupt to wake up.   __WFI(); When a packet is received over UART and interrupt is triggered so I expect the processor to just operate normally, but the system will be just frozen when I run the code. When I remove ''__WFI()'' the system is not frozen anymore but I guess I need to have this command to wait for an interrupt to wake the processor up after a sleep. Does anybody kno if I am doing anything wrong to put the processor into sleep mode and the expect it to be waken up when an interrupt is triggered? Regards, Dan

[Tesla DeLorean]

Posted on December 10, 2015 at 17:23

Make sure the PWR/BKP domain clocks are enabled, and unlocked.

Review how the library does it, at a glance clearing the bits isn't how they do it.

void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
/* Select the regulator state in STOP mode ---------------------------------*/
tmpreg = PWR->CR;
/* Clear PDDS and LPDS bits */
tmpreg &= CR_DS_MASK;
/* Set LPDS bit according to PWR_Regulator value */
tmpreg |= PWR_Regulator;
/* Store the new value */
PWR->CR = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP;
/* Select STOP mode entry --------------------------------------------------*/
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
}