Understanding STM32F103C8 AD Vref and AD range.

[pilot]

Do I understand the datasheet correctly when I believe the internal 2.1v reference is something internal, and the AD is still operating within VCC/3.3v as upper limit?

Copilot suggested this: 

// Enable ADC1 and configure it

RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // Enable ADC1 clock

ADC1->CR2 |= ADC_CR2_ADON; // Turn on ADC1

// Configure ADC1 to use the internal reference voltage (1.2V)

ADC1->CR2 |= ADC_CR2_TSVREFE; // Enable internal reference voltage

ADC1->SMPR2 |= ADC_SMPR2_SMP0; // Set sample time for channel 0 (PA0)

// Calibrate ADC1

ADC1->CR2 |= ADC_CR2_CAL; // Start calibration

while (ADC1->CR2 & ADC_CR2_CAL); // Wait for calibration to complete

Calibrate/wait for calibration ? - do I actually use the internal VREF, and the max input is corrected for up to 3.3v ?

[gbm]

Read The Fine Docs. The Vref in STM32 is not what you typically call Vref in ADC world.

The ADC reference (full range) voltage is Vdd. Vref is a known, fixed voltage, much lower than Vdd, possible to measure with ADC. In all the newer STM32 series, its Vref ADC readout value at a specified Vdda is stored by ST in System ROM (actually OTP Flash), so that you can get the precise value of Vdda without the external precise reference (unfortunately it's not the case for F1 series).

[pilot · Accepted solution]

Yes, I've read - among other things confusing things like this:

-------------------

2.3.9: Power supply schemes:

VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively

--------------------

VSSA and VDDA are "external analog poower supply"

at the same time they  "must be connected to VDD and VSS"

This makes little sense to me, I am making 3.3v from up to 53v  switching down with a small switcher (300mA)

Decent filtering, but meybe it indicates that I should stepdown to 4v, then linear-regulate down to 3v3.

And what I miss is how to get a repeatable AD performance, if my 3.3v regulator adds 50mV during certain condtitions, what will compensate to make the AD results good?  

and do I need to do something in software, or is it done automatically?

"

So on LQFP VREF- and VREF+ are internally connected.

[gbm]

They may be connected to Vdd/GND via some filters - LC or RC (especially Vdd). Esp. with noisy Vdd, you should maybe add RC or LC with 10 uF + 100 nF on Vdda. Another option is what you describe above - to use buck regulator outputting ca. 4 V, then LDO to 3.3 V or maybe even two (a separate one for Vdda).

On non-F1 series of STM32 you may measure the Vdda voltage dynamically based of ADC Vref readout, using the calibration data from System ROM. F1 series has no such calibration data, so you must rely on the accuracy of Vdda value provided by voltage regulator.

[pilot]

Changing VDD from 3.3v to 3.36v   while ad is connected to 1.6161 voltage source:

AD reads 2005-2006 at 3.3v

AD reads 1999-2000 at 3.36v  

So it is not really fully compensating for the change in input voltage.

[gbm]

It's a microcontroller, not high-accuracy ADC. Don't expect too much from it. I am surprised you are getting fluctuations of only 1 LSB value. 2..3 LSbits are quite typical.