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Unable to write ''DWT->CTRL''

Andrew1
Associate II
Posted on November 02, 2015 at 14:30

Hi,

I want to get CPU cycle counter (DWT->CYCCNT) and uUnable to write DWT_CTRL register (value is always 0x40000000).

  /* Enable TRC */

  CoreDebug->DEMCR &= ~0x01000000;

  CoreDebug->DEMCR |= 0x01000000;

  /* Reset counter */

  DWT->CYCCNT = 0;

  /* Enable counter */

  DWT->CTRL &= ~0x00000001;

  DWT->CTRL |= 0x00000001;

How to solve this problem?

I use ''System Workbench for STM32'' IDE and ''stm32f746g-discovery'' board

PS: Command ''mww 0xe0001000 1'' for openocd works, and value for DWT_CTRL becomes 0x40000001

#stm32f746g-dwt-cyccnt
5 REPLIES 5
Posted on November 02, 2015 at 15:19

There is perhaps some unlocking sequence required.

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claudiolanconelli
Associate
Posted on November 02, 2015 at 18:09

Try this:

// CoreSight Lock Status Register lock status bit

#define DWT_LSR_SLK_Pos                1

#define DWT_LSR_SLK_Msk                (1UL << DWT_LSR_SLK_Pos)

// CoreSight Lock Status Register lock availability bit

#define DWT_LSR_SLI_Pos                0

#define DWT_LSR_SLI_Msk                (1UL << DWT_LSR_SLI_Pos)

// CoreSight Lock Access key, common for all

#define DWT_LAR_KEY                    0xC5ACCE55

static inline void dwt_access_enable(bool ena)

{

    uint32_t lsr = DWT->LSR;

    if ((lsr & DWT_LSR_SLI_Msk) != 0)

    {

        if (ena)

        {

            if ((lsr & DWT_LSR_SLK_Msk) != 0)    //locked: access need unlock

                DWT->LAR = DWT_LAR_KEY;

        }

        else

        {

            if ((lsr & DWT_LSR_SLK_Msk) == 0)    //unlocked

                DWT->LAR = 0;

        }

    }

}

Andrew1
Associate II
Posted on November 03, 2015 at 06:10

Thanks for response, it works!

manuel239955
Associate II
Posted on November 12, 2015 at 13:16

Thats odd,

i could not write to it either, but writing to it at the beginning before enabling the CPU-Cache did the trick for me. I did not need to unlock it. I thought maybe it was cached or something and didnt look further into it.

why could that be?

wenbin
Associate II
Posted on November 12, 2015 at 13:58

Hi, I use the same board. The following codes work in my application. (They are placed after the system clock configuration)

  /*  Enable use of the trace and debug blocks (including DWT) */

  CoreDebug->DEMCR |= 0x01000000;

  /* Initialize DWT Current PC Sampler Cycle Count Register to 0 */

  DWT->CYCCNT = 0;

  /* Enable the CYCCNT counter*/

  DWT->CTRL |= 0x00000001;