Unable to get 0 or 100% duty cycle in up-counter mode

[PBana.2]

Dear community

I am new STM32G4 family bu i have several years of experience with C2000 form competitor TI. I would like to use STM32G4 controller in new project but i have lots of problems. I have read AN4539 HRTIM cookbook and HRTIM chapter in Reference manual and tested examples form CubeMx

I set my timer,

SETx1R -> PRD -> Period event set output to high state

RSTx1R -> CMP1 -> Compare equal event reset output to "low" state

I update my duty cycle with values in range from 0 do Period (PERCR Register)

When CMP1

= 0 -> Output is set 1!!

I try to analyse priorities

Period set 1 but Cmp1 has higher priority and should force 0 because

CMP3->CMP2->CMP1->PRD, but the output has not changed to 0.

Null duty cycle mode ignores forcing output to 0?

According to AN4539 figure 12 buck-boost converter is similar (but period set, cmp1 reset). In this situation 100% duty cycle does not work.

I have also tested example from cube library but also it does not work with 0-100% duty cycle in the same way.

How to set the timer properly Set Reset to get working with 0 and PERCR values and getting 0 and 100%. The examples form cube does not work and i observe the same issue.

[Bubbles]

Hi @PBana.2​,

yes I confirm, there are limitations on the compare registers value, depending on CKPSC value it's possible to get 3 pulses from the extreme, but not any closer. Not by normal means. To get a flat 1 or flat 1 on the output, you can for example use the break feature as a workaround.

BR,

J

[PBana.2]

Thanks @JHOUD for your answer.

But has higher priority CMP1 -> PRD and the reset event should clear. (Somewhere in documentation i have read that if two event occurs in the same time the reset event has priority)

According to Reference manual

"The compare value must be either null or above or equal to 3 periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

The null value is programmed following the use case described in Section : Null duty cycle exception case."

According to Null duty cycle chapter

"However, it is possible to skip an output pulse and have a null duty cycle by simply writing a

null value in the following two registers: HRTIM_TIMxCMP1 and HRTIM_TIMxCMP3, if and

only if the following conditions are met:

• the output SET event is generated by the PERIOD event
• the output RESET if generated by the compare 1 (respectively compare 3) event
• the compare 1 (compare 3) event is active within the timer unit itself, and not used

for other timing units

For any other use case, this can be done by programming the SET and RESET events with

the very same compare values, above 3 periods of the fHRTIM clock.

"

It means that if my case the CKPSC[2:0] is equal 0 (max clock frequency)

The minimum value of CMP1 should be not less then 0x60(96 dec) and in this case i should get 0 (not 1) on the output? In different words should i limit the duty in rage from 0x60 to PRD to get true 0...100% duty cycle?

But according to Null duty chapter (cited above) i can just write 0 value.

Could You explain me how the Null Duty Cycle works in this case?

Where i can more details about "break" that you have mentioned?

Thanks for your patience because i really don't get it.