Unable to adjust RTC or TAMP backup registers on STM32U585QIIbQ, any suggestions? I haven't seen any details in documentation as to why, and have been trying things for a few days.

[SSaunders]

I have tried the HAL without success - It seems to hard fault when initializing RTC.

I have privilege disabled, and trust zone disabled,

Unable to access any RTC or TAMP registers.

Here is a minimal example of code, including the snippets of misc things I've tried. (EX: the undocumented register, I have tried both enabled and not, and in various different places. - Similar story for any other snippets) I've just been using breakpoints to verify code gets hit correctly.

#include "stm32u585xx.h"
 
int main(){
    volatile uint32_t ulCounter = 0;
    
    //Turn on AHB3 pwrEn
    RCC->AHB3ENR |= RCC_AHB3ENR_PWREN ;
    
    //Set DBPR
    PWR_NS->DBPR |= PWR_DBPR_DBP;
    
    //Backup ram seems to work here:
    uint32_t* BKPRAM = (uint32_t*) BKPSRAM_BASE_NS;
    BKPRAM[0] = 0;
    while(BKPRAM[0] <= 64)
      BKPRAM[0]++;
    
    //Stop RTC
    RCC->BDCR &= ~RCC_BDCR_RTCEN;
   
    //Turn on LSION
    RCC->BDCR |= RCC_BDCR_LSION;
    
    //Check LSION is working
    while((RCC->BDCR & RCC_BDCR_LSIRDY) == 0)
      ulCounter++;
    
    //Reset backup domain
    RCC->BDCR |= RCC_BDCR_BDRST;
    for(int i = 0; i <= 20; i++)
      ulCounter++;
    
    //unset reset
    RCC->BDCR &= ~RCC_BDCR_BDRST;
    for(int i = 0; i <= 20; i++)
      ulCounter++;
    
    //Set RCC to LSI
    RCC->BDCR &= ~RCC_BDCR_RTCSEL;
    RCC->BDCR |= RCC_BDCR_RTCSEL_1;
    
    //RTC ON
    RCC->BDCR |= RCC_BDCR_RTCEN;
    
    //Enable RTC write
    RTC->WPR = 0xCA;
    RTC->WPR = 0x53;
    
    //Enabe some undocumented RCC_APB3ENR_RTCAPBEN
    RCC->AHB3ENR |= RCC_APB3ENR_RTCAPBEN;
    
    //Try to set BKP0R
    while(TAMP->BKP0R != 0xDEADBEEF)
      TAMP->BKP0R = 0xDEADBEEF;
    
    //Check if we ever get here
    while(1)
      ulCounter++;
}

[waclawek.jan]

//Enabe some undocumented RCC_APB3ENR_RTCAPBEN

That surely has to go before writes to RTC->WPR. Move it to the very beginning, as there may be significant delay between the write to RCC register and actual enable to happen. Same applies to the PWR enable in RCC and write to PWR register.

Read back registers which can be read back (i.e. not RTC_WPR, but certainly RCC_BDCR) and check they contain what you think they should.

Did you ever try this on some "normal" STM32?

JW

[SSaunders]

I've been using the IAR debugger to track and monitor registers, and have checked/validated the PWR and RCC registers being modified/set correctly.

I have also tried having that undocumented RCC register to the very beginning... I suppose I could make a quick script that tries all combinations of those snippets and checks if any of them work.

The code I'm porting over is from an STM32H7, which is known to be working. There isn't a WPR register, nor any TrustZone stuff. There is some tamper logic though. But editing the backup registers works after the RCC PWR EN, and the DBP value - the exact same as where the current backup registers work.

I can get access to an L board, and can try on that.

Thanks for the reply