Two NUCLEO-H755ZI-Q boards acting differently

[SoCalJim]

I have two NUCLEO-H755ZI-Q boards and I’m trying to run the SPI_FullDuplex_ComIT example on both.

One board breaks here (whether the software is built for master or slave):

The other board has no problem (whether the software is built for master or slave).

Any ideas?

[SofLit]

Hello,

Check if you have disabled CM4 in the option byte.

[SoCalJim]

BCM4 was set. I cleared it using:

./STM32_Programmer_CLI -c port=SWD -ob BCM4=0x0

I verified it’s clear. Unfortunately, the problem persists.

I looked at the working board and found both BCM4 and BCM7 are set, just like non-working board. The command

STM32_Programmer_CLI -c port=SWD -ob displ

showed no differences between the boards.

[SofLit]

Try to use STM32CubeProgrammer and check if the CM4 is enabled in the option byte.

[SoCalJim]

      -------------------------------------------------------------------
                       STM32CubeProgrammer v2.18.0
      -------------------------------------------------------------------

ST-LINK SN  : 0048001B3433510A37363934
ST-LINK FW  : V3J15M7
Board       : NUCLEO-H755ZI-Q
Voltage     : 3.29V
SWD freq    : 8000 KHz
Connect mode: Normal
Reset mode  : Software reset
Device ID   : 0x450
Revision ID : Rev V
Device name : STM32H7xx
Flash size  : 2 MBytes
Device type : MCU
Device CPU  : Cortex-M7/M4
BL Version  : 0x91


UPLOADING OPTION BYTES DATA ...

  Bank          : 0x00
  Address       : 0x5200201c
  Size          : 308 Bytes

██████████████████████████████████████████████████ 100%


OPTION BYTES BANK: 0

   Read Out Protection:

     RDP          : 0xAA (Level 0, no protection)

   BOR Level:

     BOR_LEV      : 0x0 (reset level is set to VBOR0)

   User Configuration:

     IWDG1_SW     : 0x1 (Independent watchdog is controlled by software)
     IWDG2_SW     : 0x1 (Independent watchdog is controlled by software)
     NRST_STOP_D1 : 0x1 (STOP mode on Domain 1 is entering without reset)
     NRST_STBY_D1 : 0x1 (STANDBY mode on Domain 1 is entering without reset)
     FZ_IWDG_STOP : 0x1 (Independent watchdog is running in STOP mode)
     FZ_IWDG_SDBY : 0x1 (Independent watchdog is running in STANDBY mode)
     SECURITY     : 0x0 (Security feature disabled)
     BCM4         : 0x0 (CM4 boot disabled)
     BCM7         : 0x1 (CM7 boot enabled)
     NRST_STOP_D2 : 0x1 (STOP mode on Domain 2 is entering without reset)
     NRST_STBY_D2 : 0x1 (STANDBY mode on Domain 2 is entering without reset)
     SWAP_BANK    : 0x0 (after boot loading, no swap for user sectors)
     IO_HSLV      : 0x0 (Product working in the full voltage range, I/O speed optimization at low-voltage disabled)

   Boot address Option Bytes:

     BOOT_CM7_ADD0: 0x800  (0x8000000)
     BOOT_CM7_ADD1: 0x1FF0  (0x1FF00000)
     BOOT_CM4_ADD0: 0x810  (0x8100000)
     BOOT_CM4_ADD1: 0x1000  (0x10000000)

   PCROP Protection:

     PROT_AREA_START1: 0xFF  (0x800FF00)
     PROT_AREA_END1: 0x0  (0x80000FF)
     DMEP1        : 0x0 (Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs)
     PROT_AREA_START2: 0xFF  (0x810FF00)
     PROT_AREA_END2: 0x0  (0x81000FF)
     DMEP2        : 0x0 (Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs)

   Secure Protection:

     SEC_AREA_START1: 0xFF  (0x800FF00)
     SEC_AREA_END1: 0x0  (0x80000FF)
     DMES1        : 0x0 (Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs)
     SEC_AREA_START2: 0xFF  (0x810FF00)
     SEC_AREA_END2: 0x0  (0x81000FF)
     DMES2        : 0x0 (Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs)

   DTCM RAM Protection:

     ST_RAM_SIZE  : 0x0 (2 KB)

   Write Protection:

     nWRP0        : 0x1 (Write protection not active on this sector)
     nWRP1        : 0x1 (Write protection not active on this sector)
     nWRP2        : 0x1 (Write protection not active on this sector)
     nWRP3        : 0x1 (Write protection not active on this sector)
     nWRP4        : 0x1 (Write protection not active on this sector)
     nWRP5        : 0x1 (Write protection not active on this sector)
     nWRP6        : 0x1 (Write protection not active on this sector)
     nWRP7        : 0x1 (Write protection not active on this sector)
     nWRP8        : 0x1 (Write protection not active on this sector)
     nWRP9        : 0x1 (Write protection not active on this sector)
     nWRP10       : 0x1 (Write protection not active on this sector)
     nWRP11       : 0x1 (Write protection not active on this sector)
     nWRP12       : 0x1 (Write protection not active on this sector)
     nWRP13       : 0x1 (Write protection not active on this sector)
     nWRP14       : 0x1 (Write protection not active on this sector)
     nWRP15       : 0x1 (Write protection not active on this sector)

[SofLit]

BCM4         : 0x0 (CM4 boot disabled)

The log shows that CM4 is disabled.

Please use STM32CubeProgrammer in graphical mode to enable it:

[SoCalJim]

The project is SPI_FullDuplex_ComIT_CM7:

Should CM4 be enabled? Should CM7 be enabled as well? Both are enabled on the working board.

[SofLit · Accepted solution]

---

@SoCalJim wrote:

Should CM4 be enabled? Should CM7 be enabled as well? Both are enabled on the working board.

---

Your log shows that CM4 is disabled. Both CM7 and CM4 should be enabled.

Of course CM4 needs to be activated as there is a synchronization mechanism implemented in the example:

  /* Wait until CPU2 boots and enters in stop mode or timeout*/
  timeout = 0xFFFF;
  while((__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) != RESET) && (timeout-- > 0));
  if ( timeout < 0 )
  {
    Error_Handler();
  }

If CM4 is disabled you will be infinitely looped in this while loop as CM7 is waiting for a signal from CM4 that never generated.

So please confim that by enabling CM4 (as I showed previously) the issue is solved. Or comment out that while loop.

[SoCalJim]

[SoCalJim]