Timer ISR implementation issue using STM32W108

[pmdesai1188]

Posted on March 21, 2014 at 20:04

Hello;

I am tryin to implement the Timer function using the General purpose timers TIM1 and TIM2 of the STM32W108 ARM Cortex M3 controller.Following is the initialization code for the timer 2.void timer_init(){  TIM2_PSC = 0x00;  TIM2_ARR = 0x0fff; // auto reload  TIM2_OR = 0x00;  TIM2_CNT = 0x00;  INT_TIM2CFG = 0x01;   //interrupt enable TIM1_IER  TIM2_CR1 |= 0x85;

}

For trying out the implementation following ISR for the timer has been used. void halTimer2Isr(void){  TIM2_CR1 |= 0x0;  INT_TIM2FLAG |= 0x50;  interrupt = 1;}However, while running the code the control does not transfer to the ISR.While monitoring the register contents, it was observed that the bits 0-4 of the TIM2_ISR are immediately set to 1, once I enable the timer. The same is observed even if all the configuration registers are set to 0x00 and only the timer enable bit is set.The operation was also checked in single steeping mode but the result remained the same.Can anyone please guide as to where the error could be. This the first time I am trying to implement the timer function using this processor.Thank you.Regrads;Parth Desai. #timer_isr

[Tesla DeLorean]

Posted on March 21, 2014 at 21:12

There is very little support here for the STM32W parts, even less for register level coding.

Are you sure that the handler name matches with the name of the function described in the Vector Table? See startup_stm32w108xx.c (or whatever)

[pmdesai1188]

Posted on March 22, 2014 at 03:25

Thanks Clive1.

I had checked the startup file. The ISR function name was defined based on the handler name.Also, the Timer ISR register is setting the capture/compare bits as well where as I haven't defined to enable those status bits in the code. I am only using the update event bit to check if the timer has overflown.Is there any specific procedure to be followed or any specific commands / definitions to be made in order to transfer the control of the execution to the ISR? 

[Tesla DeLorean]

Posted on March 22, 2014 at 03:44

You'd need to enable the interrupt in the NVIC

[pmdesai1188]

Posted on March 22, 2014 at 03:53

Are you talking about the Interrupt Set Enable register of the NVIC?

The standard ARM cortex M3 reference technical documentation does have its details though which I had checked but I could not find any such register description in the documentation of STM32W108. Where would I find details of the NVIC interrupt set registers? There is a regs.h file which defines the addresses for all registers. It contains some NVIC register definition but I am unable to understand which registers should I be updating and to what value?

[pmdesai1188]

Posted on March 22, 2014 at 04:15

I found these lines of code in one of the header files:

  //Provide a default NVIC configuration file.  The build process can  //override this if it needs to.  #ifndef NVIC_CONFIG    #define NVIC_CONFIG ''hal/micro/cortexm3/nvic-config.h''  #endifwhat does this mean?There was no nvic-config.h file in the folder path given in the code.

[Tesla DeLorean]

Posted on March 22, 2014 at 15:52

I'm familiar with the standard FW library

http://www.st.com/web/catalog/mmc/FM141/SC1608/SS909/PF245381

http://www.st.com/web/en/catalog/tools/PF258146

[pmdesai1188]

Posted on April 23, 2014 at 03:18

Hi clive;

Thanks for all the suggestions. The problem was in the definition of NVIC Set register as you rightly pointed out. I was not able to find the NVIC Set register, as it was not mentioned in the datasheet. So, had verified it in the Cortex M3 documentation.Thanks Again.Regards;Parth.