Timer Double Interrupt?

[picguy]

Posted on August 27, 2008 at 18:49

Timer Double Interrupt?

[picguy]

Posted on May 17, 2011 at 12:43

The attached assembly code fragment shows my setup for timer3. It is used in my application to make a 1 KHz up counter in RAM.

It appears that simply moving some code around changes the observed behavior of my very simple ISR. When I zero the status register at the top of the ISR everything works as expected. But simply moving 4 lines of code changes things. The change is a double interrupt. If I had to guess I would say that the short delay makes a pending timer3 interrupt before my code can clear TIM_SR. This happens on my STM3210E-EVAL board and based on symptoms on my STM32-SK board from IAR. (My board from IAR has one of those recalled “B� processors. Although I have yet to see what is funny about that CPU.)

[lanchon]

Posted on May 17, 2011 at 12:43

it's highly suspect that this is the cause:

http://www.st.com/mcu/forums-cat-7042-23.html your store: movs r1,#0 ;tell the timer we saw its int str r1,[r0,#TIM_SR] is being buffered and executed after the return from the ISR, causing a second int. two things should hold true: 1) reading TIM_SR after the write should fix the problem. 2) reading the int pending bit in the timer should reveal that in the second int, no timer int is really pending. this is interesting. what clock frequencies are you using for TIM3's APB, AHB and core? it's an excellent opportunity to test these things: 1) that a read to *any* register going through the same AHB/APB bridge will flush the write. (and that a read on the other bridge doesn't, as a control test.) 2) that any write going through the same AHB/APB bridge will flush the write. (and that a write on the other bridge doesn't, as a control test.)