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Timer CC interrupt flags are set when CC interrupts are not enabled

ZJing
Associate III

Hi all,

 

I am using TIM1 as PWM output generator, and TIM15 and TIM16 as general counters. A problem has occurred where the TIM15 CC1 and CC2 interrupt flags would become set after initialization, thus triggering the TIM15 interrupt. However, both the CC1 and CC2 ITs are not enabled. Why would they still become set?

 

TIM1 CC flags have the same behavor: They all become set after initialization while none of the CC interrupts are enabled.

 

Please see TIM15 init code:

/*TIM15 Init*/
LL_TIM_Init(TIM15, &timer500ms);
LL_TIM_SetOnePulseMode(TIM15,LL_TIM_ONEPULSEMODE_SINGLE);
LL_TIM_CC_DisableChannel(TIM15, LL_TIM_CHANNEL_CH1|LL_TIM_CHANNEL_CH2);
LL_TIM_EnableIT_UPDATE(TIM15);
NVIC_EnableIRQ(TIM1_BRK_TIM15_IRQn);

 

Init code of the other 2 timers:

/*TIM1 Init*/
	LL_TIM_InitTypeDef TIM_InitStruct = {0};
	LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
	LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct = {0};


	TIM_InitStruct.Prescaler = 80;
	TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
	TIM_InitStruct.Autoreload = 138;
	TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
	TIM_InitStruct.RepetitionCounter = 0;
	LL_TIM_Init(TIM1, &TIM_InitStruct);

	LL_TIM_EnableARRPreload(TIM1);
	LL_TIM_OC_EnablePreload(TIM1, LL_TIM_CHANNEL_CH4);

	TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_PWM1;
	TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
	TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
	TIM_OC_InitStruct.CompareValue = 69;
	TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
	TIM_OC_InitStruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW;
	TIM_OC_InitStruct.OCNIdleState = LL_TIM_OCIDLESTATE_LOW;

	LL_TIM_OC_Init(TIM1, LL_TIM_CHANNEL_CH4, &TIM_OC_InitStruct);
	LL_TIM_OC_DisableFast(TIM1, LL_TIM_CHANNEL_CH4);
	LL_TIM_SetOCRefClearInputSource(TIM1, LL_TIM_OCREF_CLR_INT_NC);
	LL_TIM_DisableExternalClock(TIM1);
	LL_TIM_ConfigETR(TIM1, LL_TIM_ETR_POLARITY_NONINVERTED, LL_TIM_ETR_PRESCALER_DIV1, LL_TIM_ETR_FILTER_FDIV1);
	LL_TIM_SetTriggerOutput(TIM1, LL_TIM_TRGO_RESET);
	LL_TIM_SetTriggerOutput2(TIM1, LL_TIM_TRGO2_RESET);
	LL_TIM_DisableMasterSlaveMode(TIM1);

	TIM_BDTRInitStruct.OSSRState = LL_TIM_OSSR_DISABLE;
	TIM_BDTRInitStruct.OSSIState = LL_TIM_OSSI_DISABLE;
	TIM_BDTRInitStruct.LockLevel = LL_TIM_LOCKLEVEL_OFF;
	TIM_BDTRInitStruct.DeadTime = 0;
	TIM_BDTRInitStruct.BreakState = LL_TIM_BREAK_DISABLE;
	TIM_BDTRInitStruct.BreakPolarity = LL_TIM_BREAK_POLARITY_HIGH;
	TIM_BDTRInitStruct.BreakFilter = LL_TIM_BREAK_FILTER_FDIV1;
	TIM_BDTRInitStruct.Break2State = LL_TIM_BREAK2_DISABLE;
	TIM_BDTRInitStruct.Break2Polarity = LL_TIM_BREAK2_POLARITY_HIGH;
	TIM_BDTRInitStruct.Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1;
	TIM_BDTRInitStruct.AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_ENABLE;
	LL_TIM_BDTR_Init(TIM1, &TIM_BDTRInitStruct);

	LL_TIM_CC_EnableChannel(TIM1, LL_TIM_CHANNEL_CH4); 				//This line was NOT included in automatically generated code, and PWM output would not work without this line!!!
	LL_TIM_DisableIT_UPDATE(TIM1);
	LL_TIM_DisableIT_BRK(TIM1);

	/*TIM16 Init*/
	LL_TIM_Init(TIM16, &timer50ms);
	LL_TIM_SetOnePulseMode(TIM16,LL_TIM_ONEPULSEMODE_SINGLE);
	LL_TIM_EnableIT_UPDATE(TIM16);
	NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);		

 

 

 

1 REPLY 1
gbm
Lead II

The CCxIF flags are not dependent on CCxIE bits. A CCxIF flag is set in compare mode at the beginning of a timer period if CCRx is 0 or > ARR. The flag may be tested in software without the interrupts being used.