thumb and thumb2 with STM32L1

[gfoujanet]

Posted on February 21, 2013 at 17:15

I would like to know if the STM32L1 based on Cortex-M3, supports and THUMB and THUMB2 modes?

Or if when we build with the command --cpu_mode thumb, it's the thumb2 instructions set which is used....Thanks, #stm32-stm32l1-thumb-build

[Tesla DeLorean]

Posted on February 21, 2013 at 19:20

It runs Thumb2 of which Thumb is a subset, it will not run ARM 32-bit instructions.

For GNU I've used -mcpu=cortex-m3 -mthumb You helpfully don't mention a tool chain, I'll guess it's IAR

--cpu_mode thumb

--endian=little

--cpu=Cortex-M3

[gfoujanet]

Posted on February 21, 2013 at 21:14Ok, thanks.So if I understand,  if we build with --cpu_mode thumb, it's the thumb2 set which is used...Do you know some option with IAR to optimize the speed code (other than -Ox and no_xxxxx).Thanks

[Tesla DeLorean]

Posted on February 21, 2013 at 21:59

I think the --cpu=Cortex-M3 is the MOST critical aspect to getting Thumb2 opcodes, as it is the option that infers the correct ISA to be used, I think it would implicitly set Thumb as the Mx series doesn't support 32-bit ARM, interleaving, etc. And the M0 has an even smaller subset of instructions to work from.

I think the -Oxx and --no_xxxx are indeed the primary ways to control optimization, for the M4 you'd be able to turn the FPU instruction generation on/off. What are you trying to optimize, and what's the issue with that optimization at this time? Consider your algorithm, if you can unroll loops, or use parallelism, or recode in a way that lends itself to machine optimization. Consider also assembler. Optimizers are rule driven, they don't understand algorithms.

http://supp.iar.com/FilesPublic/UPDINFO/004916/arm/doc/EWARM_DevelopmentGuide.ENU.pdf