Temporarily suspending SPI

[andyturk]

Posted on December 29, 2012 at 01:28

I've got a mixed-signal board with an LCD connected through noisy SPI lines. When the display is being updated, the analog readings are all over the place. In addition to improving the layout of the board, I'm also looking at suspending SPI activity while the ADCs are active.

I've got this more-or-less working at the moment by simply clearing the SPI's enable flag just before kicking off the ADCs and re-enabling it in the completion callback. To guard against an SPI transaction that's already underway, the ADC collects an extra filler sample at the beginning of it's run.However, in 25.3.8 of RM0008 it says, ''… disabling the SPI and entering the Halt mode while a transfer is ongoing can cause the current transfer to be corrupted …'', which is rather ominous.I haven't observed any corruption, but maybe that's just dumb luck. Or maybe the warning is more specifically to do with ''halt mode'' (which I'm assuming refers to the core, not just the SPI peripheral).Have others throttled SPI like this before? How likely is this to blow up somewhere down the road with silicon revisions or other stuff hanging off the SPI bus?PS. This is an F103 mcu and I'm using SPI2 in full-duplex master mode.PPS. Oops, this got posted in the wrong forum. Sorry.

[andyturk]

Posted on December 30, 2012 at 03:55

Err, well maybe here's some ''corruption'':

http://turkish.smugmug.com/Electronics/Sync/i-rdqjtJb/0/O/NewFile8.jpgThe yellow trace is showing a GPIO that goes high just before the EN bit of the SPI is cleared. It goes low again after the ADC is done reading.The blue trace is the MOSI line. Except for that exponential ramp, the SPI is quiet when it's supposed to be. SCK is also dark during the time when the yellow trace is high, but I only have a two channel scope and can't show both at the same time.That ramp looks rather suspect though. It's like the internal MOSI line went high-Z when the SPI was disabled and a weak pull-up is gradually bringing the line up to VDD. This behavior doesn't seem to cause any problems with the LCD I'm using, but it seems out of place.

[andyturk]

Posted on December 30, 2012 at 03:56

Err, well maybe here's some ''corruption'':

http://turkish.smugmug.com/Electronics/Sync/i-rdqjtJb/0/O/NewFile8.jpg The yellow trace is showing a GPIO that goes high just before the EN bit of the SPI is cleared. It goes low again after the ADC is done reading. The blue trace is the MOSI line. Except for that exponential ramp, the SPI is quiet when it's supposed to be. SCK is also dark during the time when the yellow trace is high, but I only have a two channel scope and can't show both at the same time. That ramp looks rather suspect though. It's like the internal MOSI line went high-Z when the SPI was disabled and a weak pull-up is gradually bringing the line up to VDD. This behavior doesn't seem to cause any problems with the LCD I'm using, but it seems out of place. ________________ Attachments : NewFile8.bmp : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HzLI&d=%2Fa%2F0X0000000bO5%2F_1Rlot.ESRvleGBm3oFvrQPhSp45Fs_2aAvQCgY48Bo&asPdf=false

[crt2]

Posted on December 31, 2012 at 12:32

How about check your pin configuration - pullup at gpio might be also something to count it in on either side because that seems like RC particle ;)

Maybe put it to sleep a bit longer and see where it ''floats''