Systick default clock setting for stm32f3discovery_fw

[andreaspiezia9]

Posted on October 08, 2013 at 10:42

Hi all,

I�m starting to deal with STM32F30 discovery.

I need confirmation about my assertion on default clock configuration for the stm32f3discovery_fw.In file system_stm32f30x.c the define PLL_SOURCE_HSE_BYPASS is uncommented

// HSE bypassed with an external clock (8MHz, coming from ST-Link) used to clock the PLL, and the PLL is used as system clock source

In this case the function SystemInit() calls the functions SetSysClock():

&sharpelif defined (PLL_SOURCE_HSE_BYPASS)

  /* HSE oscillator bypassed with external clock */   

  RCC->CR |= (uint32_t)(RCC_CR_HSEON | RCC_CR_HSEBYP);

The same function sets HCLK = SYSCLK = PCLK2 = PCLK1 and PLLCLK = HSE * 9 = 72 Mhz and then Select PLL as system clock source, this meanse that HCLK =  72 Mhz

SysTick_Config() configure the SysTick Counter clock source to be Core Clock Source (HCLK).

At the end I understood that  SysTick Counter clock is  72 Mhz.

This means that SysTick_Config(SystemCoreClock / 1000) give an interrupts every 72000 clock cycle, that is an interrupt every 0.1 ms , is it correct?

Your support is very appreciate.

Thanks

#stm32f3discovery_fw-systick

[Tesla DeLorean]

Posted on October 08, 2013 at 14:03

This means that SysTick_Config(SystemCoreClock / 1000) give an interrupts every 72000 clock cycle, that is an interrupt every 0.1 ms , is it correct?

1000 times a second (1 KHz) has a period of 1 ms

[andreaspiezia9]

Posted on October 09, 2013 at 11:55

Thank you Clive.

The rest of assertions seems correct, right?

[Tesla DeLorean]

Posted on October 09, 2013 at 14:21

Other than I'd expect PCLK1 (APB1) to be 36 MHz. At the Reagan School of Engineering, we Trust, but Verify. If you have doubts about the clocks, break out a scope and check them.