SYSCLK

[41003160]

Posted on November 16, 2013 at 17:00

I read in system_stm32f4xx.c that after reset, sysclk is 168MHz. I want to creat a function delay 1s.

void Delay(void) { uint32_t i; for(i=0; i<0xA037A00; ++i)   // A037A00 = 168.000.000 { }   }.Who can explain for me: how many machine cycle for ++i  and {}if you can, help me creat a function delay.thank for reading!

[Tesla DeLorean]

Posted on November 16, 2013 at 17:26

Doesn't it reset to 16 MHz (HSI)? SystemInit() might set it to something else prior to main() being called.

Look at the code the compiler generates (listing or code file, or disassemble it). You might want i as volatile so the optimizer doesn't throw out the code. Using software delay loops like this is a fools choice, you are better to use timers and counter (TIMx, SysTick). If you must dwell in a loop, consider looking at a free running timer, or the core's cycle counter.

[41003160]

Posted on November 16, 2013 at 17:36

Dear !

Thank for answer!After each device reset the HSI (16 MHz) is used as system clock source.*-----------------------------------------------------------------------------  *        SYSCLK(Hz)                             | 168000000  *-----------------------------------------------------------------------------  *        HCLK(Hz)                               | 168000000  *-----------------------------------------------------------------------------I just copy from system_stm32f4xx.c. STM32f4 is new MCU for me. I know if use timer is better than delay by for or while loop. but I want to know exactly. Thanks!

[Tesla DeLorean]

Posted on November 16, 2013 at 19:06

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/compensating%20latencies%20on%20STM32F4%20interrupts&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&cu...

The DWT_CYCCNT is also useful for benchmarking loops and code. If you compare to a value, interrupts and cycle variations (buses, contention, caching) shouldn't materially impact the total delay.